AW00083108000
Pixel Data Transmission Sequence with the 1X2-1Y Tap Geometry
When the camera is not transmitting valid data, the frame valid, line valid, and data valid bits sent
on each cycle of the pixel clock will be low. Once the camera has acquired an image and has read
the pixel data out of the imaging sensor, it will begin transmitting the data (see Figure 5):
(1) - (2):
On the pixel clock cycle where frame data transmission begins, the frame valid bit will become
high.
(1) (2)
TIMING DIAGRAMS ARE NOT DRAWN TO SCALE.
H = height = the last line in the image (e.g., line 1024 on a camera with the AOI set to 1024 x 1024)
W = width = the last pixel in the line (e.g., pixel 1024 on a camera with the AOI set to 1024 x 1024)
A - F: see next page
Fig. 5: Pixel Data Output Timing for the 1X2-1Y Tap Geometry
(2) - (3):
Two pixel clock cycles later, the line valid and data valid bits will become high and data
transmission for line 1 begins. Two data streams, D0 and D1, are transmitted in parallel
during this clock cycle.
On this clock cycle, data stream D0 will transmit data for pixel 1 in line 1 and data stream D1
will transmit data for pixel 2 in line 1. Depending on the pixel format selected, the pixel data
will be at 12, 10, or 8 bit depth.
On the next pixel clock cycle, the line valid and data valid bits will still be high.
On this clock cycle, data stream D0 will transmit data for pixel 3 in line 1 and data stream D1
will transmit data for pixel 4 in line 1.
Basler aviator Camera Link
(3)
Pixel Data Output
(4)
15
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