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EVM Setup
5.3.1
Startup
Figure 2
to
Figure 5
5
V
V
LDO_IN
AC
V
V
LDO_OUT
PG
4
3
2
1
0
-1
0
0.1
0.2
0.3
0.4
Time (sec)
Figure 2. Startup: 120-V
5
V
V
LDO_IN
AC
V
V
LDO_OUT
PG
4
3
2
1
0
-1
0
0.1
0.2
0.3
0.4
Time (sec)
Figure 4. Startup: 230-V
In
Figure
6, the power-fail detect (PFD) trace and resistor divider was placed close to the AC_P pin and as
a result the power-fail (PF) signal glitches whenever there is a shunt event; see the
Description section for details on the device active bridge control.
8
TPS7A78EVM-011 Evaluation module
show various start-up plots for the TPS7A78EVM-011.
1000
800
600
400
200
0
-200
0.5
0.6
0.7
0.8
0.9
1
Half-Bridge (HB) and 27-mA
AC
Load Current
2000
1600
1200
800
400
0
-400
0.5
0.6
0.7
0.8
0.9
1
Half-Bridge (HB) and 27-mA
AC
Load Current
6
V
LDO_OUT
V
PF
5
4
3
2
1
0
0
1
2
3
Figure 6. PF Signal Glitch
Copyright © 2019, Texas Instruments Incorporated
5
V
LDO_IN
V
LDO_OUT
4
3
2
1
0
-1
0
0.1
Figure 3. Startup: 120-V
5
V
LDO_IN
V
LDO_OUT
4
3
2
1
0
-1
0
0.1
Figure 5. Startup: 230-V
Figure 6
V
AC_P
4
5
6
7
8
9
Time (ms)
V
AC
V
PG
0.2
0.3
0.4
Time (sec)
Full-Bridge (FB) and 55-mA
AC
Load Current
V
AC
V
PG
0.2
0.3
0.4
Time (sec)
Full-Bridge (FB) and 55-mA
AC
Load Current
TPS7A78
Feature
shows the PF signal glitch.
48
40
32
24
16
8
0
10
SBVU048 – March 2019
Submit Documentation Feedback
www.ti.com
1000
800
600
400
200
0
-200
0.5
2000
1600
1200
800
400
0
-400
0.5
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