Table of Contents
Advertisement
VCC_Core, VCCGT
8
7
Intel SKYLAKE IMVP8 POWER CKT - 2+1 PHASE
Gary_D02 for BUG solution
D
VREF_VCORE
Gary_D02 for BUG solution
VIN
C
PR55
1_1%_06
VBOOT=0.8V
FOR CV
VIN
5V
1
2
PR59
1_1%_06
PJ4
*CV-1mm
PJ3
1
2
1mm
Short
GT Max Switching Frequency=425Khz
Gary_D02 for BUG solution
VCORE
VCORE_R change to VCORE
PR268
B
100_04
PR581
*20mil_04
PR37
5
VCC_VCORE_SENSE
PJ PIN change to short
PC13
PC14
PC12
*1000p_50V_X7R_04
*1000p_50V_X7R_04
100p_50V_NPO_04
PR582
*20mil_04
5
VSS_VCORE_SENSE
PR39
PC2
100_04
*1000p_50V_X7R_04
VCCGT_R change to VCCGT
VCCGT
PR291
100_04
PR583
*20mil_04
7
VCCGT_SENSE
PJ PIN change to short
PC16
PC18
A
*1000p_50V_X7R_04
*1000p_50V_X7R_04
PR584
*20mil_04
7
VSSGT_SENSE
PR31
100_04
PC10
*1000p_50V_X7R_04
8
7
6
5
4
VCORE
IMON
GT IMON
VREF_VCORE
VREF_VCORE
PR12
PR221
0_04
0_04
PR220
33.2K_1%_04
PR11
56K_1%_04
10k ntc
RT3
RT1
100k_1%_04_NTC
EWTF02-103F3I-N
PR8
0_04
VREF_VCORE
PR10
1_04
Gary_power
change
footprint
PC1
CORE Max
Switching
Frequency=421Khz
PR54
560K_1%_06
PC25
0.22u_50V_Y5V_06
40
PR52
0_04
NC
PR50
499K_1%_06
PC23
48
TONSET
TONSET
0.22u_50V_Y5V_06
38
TONSETA
TONSETA
RT3606BE
43
45
DRVON1
PS4
SET1
12
SET1
SET2
13
GND
SET2
SET3
14
SET3
15
SETA1
SETA1
SETA2
16
SETA2
10
VSEN
PR34
10K_1%_04
43.2K_1%_04
9
PU1
RT3606BE
COMP
8
FB
PC11
82pF_50V_NPO_04
11
RGND
PR248
2.2_06
5V
VCORE_PG
PR53
PR41
10K_1%_04
PR42
18K_1%_04
10K_06
PC17
PC19
3.3VS
82p_50V_NPO_04
220p_50V_X7R_04
6
5
4
3
2
H-line 42
1.0V_VCCST
PC36
1.0V_VCCST
1u_6.3V_X5R_04
1
2
PR32
10K_04
PJ1
*CV-1mm
PR90
1
2
ALL_SYS_PWRGD
*1K_1%_04
PJ2
OPEN_4mil
Short
H_PROCHOT#
4,49
PR2
49.9_1%_04
H_CPU_SVIDCLK
4
PR3
10_04
PR1
H_CPU_SVIDDAT
4
0_04
PR4
0_04
H_CPU_SVIDALRT#
4
VR_ENABLE
PC24
0.1u_16V_X7R_04
C1
PR60
330K_1%_06
*0.1u_10V_X7R_04
VIN
PR51
100K_1%_04
Gary_D02 for BUG solution
39
DVD
5V
PSYS&OFSA
45
PWM1
PWM11
45
44
PR219
PWM2
PWM21
45
*0_04
46
PWM3
PR250
unused
floating.
*0_04
PSYS
49
26
OFSA/PSYS
OFSA/PSYS
5
PR222
ISEN1P
CSP11
45
20K_04
4
PR43
680_1%_04
CSN11
45
ISEN1N
GT
6
NO Load Offset
ISEN2P
CSP21
45
7
PR44
680_1%_04
PSYS
DISABLE
ISEN2N
CSN21
45
2
ISEN3P
3
PR244
10K_06
5V
ISEN3N
The unused ISENAxP pins are recommended to be connected to VCC
42
PWMA1
PWM12
45
41
PWMA2
unused
floating.
PC132
CSP12
45
PR46
680_1%_04
CSN12
45
PR249
10K_06
5V
5V
23
PR218
CORE
*0_04
NO Load Offset
DISABLE
OFSM
PR223
0_04
4,6,24,25,42
1.0V_VCCST
19,25,41,42,43,44,45,48,49,50,51
VIN
34,35,37,41,44,45,47,48,51,52
5V
Title
Title
Title
[46] VCC_CORE & VCCGT
[46] VCC_CORE & VCCGT
[46] VCC_CORE & VCCGT
6,48
VCCSA
8,9,19,20,21,22,24,25,26,27,28,30,32,33,36,37,38,39,40,41
3.3VS
5,45
VCORE
Size
Size
Size
Document
Document
Document
Number
Number
Number
7,45
VCCGT
Custom
Custom
Custom
SCHEMATIC1
SCHEMATIC1
SCHEMATIC1
Date :
Date :
Date :
Tuesday, October 25, 2016
Tuesday, October 25, 2016
Tuesday, October 25, 2016
3
2
Schematic Diagrams
1
D
3.3VS
4,19,23,40
Sheet 46 of 58
VCC_Core, VCCGT
C
B
A
R e v
R e v
R e v
6-71-N8500-D02
6-71-N8500-D02
6-71-N8500-D02
D02
D02
D02
Sheet
Sheet
Sheet
46
46
46
o f
o f
o f
58
58
58
1
VCC_Core, VCCGT B - 47
Advertisement
Table of Contents
