qian.mx XIAO PC User Manual page 46

Here is summarization of the key differences(get from synopsys.com)
Feature
I/O Standard
Common Packages
Command and address
bus
Command protocol and
registers
Output strobe timing
for 1600 speed bin
Aproximate relative
power
How long does it take
to exit stanby (solf-
refresh) mode and do
a read?
Estimated tupical
relative price
Typical number of
devices per memory
channel
Relevant JEDEC
standard
If it was looking for
one to show you, the
first place I would look
would be...
46
DDR3
1.5V SSTL
4 and 8 bit single-die
packages
Single data rate with
separated command
and address
Same as DDR3L
Tightly controlled by a
DLL on the DRAM chip
to within +/- 225ps of
clock
X while active, Y while
in standby
512 clock cycles
Low
8-32
JESD79-3F (July 2012)
On a DMM socketed
in a lower-end PC or
server
DDR3L
1.35V SSTL
4 and 8 bit single-die
packages
Single data rate with
separated command
and address
Same as DDR3
Tighty controlled by a
DLL on the DRAM chip
to within +/- 225ps of
clock
85% of X while active,
85% of Y while in
standby
512 clock cycles
A little higher
8-32
JESD79-3-1A (May
2013)
On a DMM socketed
in a newer laptop or
server
LPDDR3
1.2V HSUL
32-bit multi-die
packages
Double data rate with
multiplexed command
and address
Different to DDR3 ans
DDR3L
Loosely controlled (no
DLL on DRAM chip),
from 2500 to 5500 after
clock
70% of X while active,
10% of Y while in
standby
112 clock cycles
for 4GB device and
DDR1600 speed
Highest
1-4
JESD209-3B (August
2013)
Soldered directly to
the PCB of a high-end
mobile phone or tablet