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Document type:
User's Manual (MUT)
1.2. Block diagram
MICROPROCESSOR
RS232
CAENET Line
PULSE IN
+
CLK
-
I/O
NPO:
00100/98:V793x.MUTx/00
Title:
Mod. V793, ICARUS Slow Control Module
ADC
MUX
CONTROLLER
CAENET
+
-
CLOCK
LVDS
Fig. 1.1 - Block diagram of the Model V793
Filename:
V793_REV0.DOC
Revision date:
16/01/01
DAC 1
DAC 2
to A764
OUT
to V791
REG
to A764
to V791
Revision:
0
4
CON_HV[1..4]
+5V D
+5V A
-5V A
DAC1
DAC2
TEST_C
ENABLE_EVEN
ENABLE_ODD
CALIB_EVEN
CALIB_ODD
19
EN_BRD[1..19]
TEST_PULSE-
TEST_PULSE+
T_PULSE-
T_PULSE+
D R V _ 1
D R V _ 2
D R V _ 3
D R V _ 4
CLOCK+
C L O C K -
Number of
Page:
pages:
19
5
GND
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