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Caen DT5495 manual available for free PDF download: User Manual
Caen DT5495 User Manual (61 pages)
Electronic Instrumentation, Desktop Programmable Logic Unit
Brand:
Caen
| Category:
Controller
| Size: 2 MB
Table of Contents
Purpose of this Manual
2
Change Document Record
2
Symbols, Abbreviated Terms and Notation
2
Reference Documents
2
Index
4
Table of Contents
4
List of Figures
5
List of Tables
5
1 Introduction
7
Tab. 1.1: Comparison Table between V1495 and DT5495
7
Tab. 1.2: Table of Models and Related Items
8
2 Block Diagram
9
Fig. 2.1: Block Diagram
9
3 Main Components and Interconnections
10
Fig. 3.1: Main Components and Interconnections
10
USB Interface
11
Ethernet Interface
11
Main FPGA
11
User FPGA
11
Gate and Delay Generator
11
Clock Distribution
11
Fig. 3.2: the UFPGA and GDG Interface
11
4 Front Panel Connectors, Leds and Labels
12
Fig. 4.1: Front (Top) and Rear (Down) Panel View
12
Front Panel
13
Rear Panel
15
5 Technical Specifications
17
Tab. 5.1: DT5495 Specifications Table
17
Tab. 5.2: A395A Mezzanine Specifications Table
17
Tab. 5.3: A395B Mezzanine Specifications Table
18
Tab. 5.4: A395C Mezzanine Specifications Table
18
Tab. 5.5: A395D Mezzanine Specifications Table
18
Tab. 5.6: A395E Mezzanine Specifications Table
18
6 Power Requirements
19
7 Getting Started with DT5495
20
Shipping Content
20
Mezzanine Boards Installation
21
Fig. 7.1: DT5495 Motherboard with Mezzanine Boards
21
Front Panel Connector Cabling
22
Fig. 7.2: Multi-Pin Connector Pin Assignment
22
Fig. 7.3: CAEN A967 Cable Adapter
22
Power-On Configuration Sequence
23
Restore Function
23
8 Communication
24
Drivers
24
Direct USB Driver Installation
24
Fig. 8.1: DT5495 Hardware Detection
24
Fig. 8.2: USB Driver Manual Installation: Step1
25
Fig. 8.3: USB Driver Manual Installation: Step2
25
Fig. 8.4: USB Driver Manual Installation: Step3
26
Fig. 8.5: USB Driver Manual Installation: Step4
26
Fig. 8.6: USB Driver Manual Installation: Step5
27
Ethernet Configuration
28
Fig. 8.7: the Network and Sharing Center Window
28
Fig. 8.8: Properties Window of the Ethernet Network
28
Fig. 8.9: Ethernet Properties Window
29
Fig. 8.10: Properties Window of the "Internet Protocol Version (Tpc/Ipv4)
29
Web Interface
30
Fig. 8.11: Instrument Information Page of the DT5495 Web Interface
30
Fig. 8.12: Instrument Information Page of the DT5495 Web Interface
30
Software Tools
31
Caenupgrader
31
Fig. 8.13: Caenupgrader Get Firmware Release Menu
31
Fig. 8.14: Caenupgrader MFPGA Upgrade Firmware Menu
32
Fig. 8.15: Caenupgrader UFPGA Flash Memory Image Menu
33
Fig. 8.16: Caenupgrader UFPGA Upgrade Firmware Menu
33
Plulib Library
34
Fig. 8.17: CAEN Plulib Demo Application Prompt
34
9 Software Interface
35
Address Map
35
User FPGA Data Access (0X0000-0X0Fff)
35
User FPGA Register Access (0X1000-0X7Fff)
35
Tab. 9.1: DT5495 Register Address Map
35
Configuration ROM (0X8100-0X81Ff)
36
Configuration and Status Registers (0X8200-0X83Ff)
36
Tab. 9.2: ROM Address Map of the DT5495
36
Tab. 9.3: CSR Registers
36
MFPGA Firmware Revision Register
37
Software Reset Register
37
Scratch Register
37
Flash Configuration (0X8500-0X8Aff)
37
Internal Scratch SRAM(0X8C00-0X8Fff)
37
10 Firmware Development
38
Introduction
38
User FPGA I/O Ports
39
Tab. 10.1: Clock Ports Description Table
39
Tab. 10.2: Mainboard Robinson-Nugent Connector Description Table
39
Tab. 10.3: LEMO G Ports Description Table
39
Tab. 10.4: Expansion I/O Ports Description Table
39
Fig. 10.1: Caencomm Demo Java and Labview Graphical Interface
40
Tab. 10.5: A395D Mapping
40
Tab. 10.6: LED Ports Description Table
40
Tab. 10.7: Gate and Delay Generator Ports Description Table
40
Tab. 10.8: Local Bus Ports Description Table
41
Local Bus Interface
42
Fig. 10.2: Local Bus Signals at a Write Access (X8Badf00D Is Written on Register X1800)
42
Fig. 10.3: Local Bus Signal at a Read Access (X8Badf00D Is Read from Register X1800)
42
Fig. 10.4: Prefetch Mechanism
43
Gate and Delay Controller
44
General Description
44
Fig. 10.5: Gate and Delay Parameters Representation
44
Tab. 10.9: Main Parameters of the Gate and Delay Generator
44
Register Description
45
Tab. 10.10: Local Bus Registers Description for the Gate and Delay Generator Configuration
45
Example Procedures
46
Porting V1495 to DT5495
47
11 Demo Firmware
48
Demo Structure
48
Demo Setup
48
Introduction
49
Gate Pattern Demo Description
49
Register Map
49
Introduction
52
Pattern Recorder Demo Description
52
Register Description
54
DAC Demo Description
54
Introduction
56
Register Map
56
Gate and Delay Demo Description
56
12 Software Development
59
13 CAEN Support
60
Returns and Repairs
60
Technical Support Service
60
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