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THine CEL THCV231 Manual

Serdes transmitter and receiver with bi-directional transceiver
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General Description
The THCV231 and THCV236 are designed to
support video data transmission between the host and
display.
THCV231
One high-speed lane can carry up to 14bits data at a
pixel clock frequency from 12MHz to 160MHz.
THCV236
One high-speed lane can carry up to 32bit data and
3bits of synchronizing signals at a pixel clock
frequency from 6MHz to 160MHz by converting
RGB444 to YCbCr422.
The chipset, which has one high-speed data lane,
can transmit video data up to 1080p/60Hz.
The maximum serial data rate is 4.00Gbps/lane.

Block Diagram

D11-D0
HSYNC
VSYNC
CLKIN
Settings
2-wire I/F
SDA/SCL
THCV231_THCV236_Rev.2.30_E
Copyright©2016 THine Electronics, Inc.
THCV231 and THCV236
SerDes transmitter and receiver with bi-directional transceiver
THCV231
TXP
TXN
TCMP
TCMN
Controls
OSC
LDO
CAPOUT
CAPINA
CAPINP

Features

Data width selectable
Wide frequency range
AC coupling for high-speed lanes
CDR requires no external frequency reference
Wide range supply voltage from 1.7V to 3.6V
Additional spread spectrum on data stream
2-wire serial interface bridge function(400kbps)
Remote side GPIO control and monitoring
THCV231
QFN32 (5mm x 5mm) with exposed pad ground
THCV236
QFN64 (9mm x 9mm) with exposed pad ground
EU RoHS compliant
THCV236
RXP
RXN
RCMP
RCMN
Controls
OSC
LDO
1/56
D31-D0
HSYNC
VSYNC
DE
CLKOUT
Settings
2-wire I/F
SDA/SCL
CAPOUT
CAPINA
THine Electronics, Inc.
Security E

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Summary of Contents for THine CEL THCV231

  • Page 1: Contents Page General Description

    THCV231 THCV236 D11-D0 D31-D0 HSYNC HSYNC VSYNC VSYNC CLKIN CLKOUT TCMP RCMP Settings Settings TCMN RCMN Controls Controls 2-wire I/F 2-wire I/F SDA/SCL SDA/SCL CAPOUT CAPOUT CAPINA CAPINA CAPINP THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 1/56 Copyright©2016 THine Electronics, Inc. Security E...

  • Page 2: Table Of Contents

    Electrical Specification ............................38 AC Timing Diagrams and Test Circuits ......................44 PCB Layout Guideline regarding VDD and AVDD for THCV236 ..............53 Package ................................. 54 Notices and Requests ............................56 THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 2/56 Copyright©2016 THine Electronics, Inc. Security E...

  • Page 3: Pin Configuration

    HSYNC CAPOUT (TOP VIEW) TCMP TCMN CLKIN 33 EXPGND CAPINA CAPINP THCV236 (QFN 64pin) HSYNC HTPDN/SUBMODE CLKOUT LOCKN/MSSEL (TOP VIEW) CAPOUT 65 EXPGND CAPINA MAINMODE/RCMN HFSEL/RCMP D24/GPIO3 RXDEFSEL D25/GPIO4 THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 3/56 Copyright©2016 THine Electronics, Inc. Security E...

  • Page 4: Pin Description

    CO : CML Output buffer , CB : CML Bi-directional buffer I : LVCMOS Input buffer , IL : Low Speed LVCMOS Input buffer , B : LVCMOS Bi-directional buffer PWR : Power supply , GND : Ground THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 4/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 5 When GPIO0 is used as Open-Drain Output, it must be connected with a pull-up resistor to VDD. When GPIO0 is used as push pull output or input, no external component is required. THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 5/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 6 VDD. When GPIO2 is used as push pull output or input, no external component is required. CLKOUT Clock Output D31-D26 12-15,17,18 Pixel Data Output THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 6/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 7 I : LVCMOS Input buffer , IL : Low Speed LVCMOS Input buffer , O: LVCMOS Output buffer B : LVCMOS Bi-directional buffer , BO : Open-Drain LVCMOS Bi-directional buffer PWR : Power supply , GND : Ground THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 7/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 8 *1 When Field BET mode (Main-Link or Sub-Link), it functions as BETOUT output. *2 When Field BET mode (Main-Link or Sub-Link), it functions as LATEN input. *3 Through GPIO input is default on register setting THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 8/56 Copyright©2016 THine Electronics, Inc. Security E...

  • Page 9: Functional Overview

    THCV236 THCV231 10uF 10uF Power Power AVDD CAPOUT AVDD CAPOUT Supply Supply 0.1uF 0.1uF CAPINA CAPINA 0.1uF CAPINP Figure 1. Connection of CAPOUT, CAPINA, CAPINP and Decoupling Capacitor THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 9/56 Copyright©2016 THine Electronics, Inc. Security E...

  • Page 10: Power Down (Pdn1, Pdn0, Pdn)

    This function is controlled by OUTSEL pin or OUTSEL_ENABLE register and OUTSEL_SETTING register. See Table 5. Table 5. Permanent Clock Output function table (PDN1=1) OUTSEL_ OUTSEL_ Output Clock ENABLE SETTING Frequency (*1) (register) (register) 80MHz 40MHz(default) 20MHz 10MHz *1 typical value THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 10/56 Copyright©2016 THine Electronics, Inc. Security E...

  • Page 11: Spread Spectrum Clock Generator (Sscg)

    HFSEL and LFSEL settings, input clock frequency and FMOD register setting (default value 0xD). Refer to following formula.  CLKSSCG  FMOD is the frequency listed in Table 9 and Table 10. CLKSSCG THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 11/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 12 Up to 0.5 % spread at the 30kHz modulation frequency is stable for most cases. In case of using out of this range, please verify at the actual system. THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 12/56 Copyright©2016 THine Electronics, Inc. Security E...

  • Page 13: Hot-Plug Function

    LOCKN is transferred via Sub-Link line. HOST MPU can confirm LOCKN state by reading Sub-Link Master register (0x00 bit1 LOCKN). ® ® Figure 2. HTPDN, LOCKN transmission route THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 13/56 Copyright©2016 THine Electronics, Inc. Security E...

  • Page 14: Field Bet Operation

    *1 THCV231: Register setting (0x53 bit1), THCV236: Pin setting *2 Register setting (0x53 bit0, Default 0) Table 12. THCV236 Main-Link Field BET Result BETOUT Output Bit Error Occurred No Error THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 14/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 15 THCV231 THCV236 Test Pattern Test Pattern RF/BETOUT Sub-Link Checker Generator Test Point Field BET BET=1 BET_SEL=1 BET=1 BET_SEL=1 GPIO4=1 (Register) (Register) (Pin) (Register) Figure 4. Sub-Link Field BET Configuration THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 15/56 Copyright©2016 THine Electronics, Inc. Security E...

  • Page 16: Data Width And Frequency Range Select Function

    D8/RAW0 D9/RAW1 D10/RAW2 D11/RAW3 HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC (*1) VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC (*1) *1 Any signal as well as sync signal can be transmitted. THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 16/56 Copyright©2016 THine Electronics, Inc. Security E...

  • Page 17: 2-Wire Serial I/F Mode

    When 2WIRE_MODE = 01, Sub-Link Master device informs HOST MPU that Sub-Link Slave register access or remote side 2-wire serial register access has been completed by interruption (INT pin) without clock stretching. THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 17/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 18 0x25 or 0x26 or 0x2B or 0x2C (SCL) Interruption Sub-Link communication time + Sub-Link Slave side internal bus access process time Sub-Link communication time + Remote side 2-wire serial Access Time Figure 5. 2WIRE_MODE Operation THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 18/56 Copyright©2016 THine Electronics, Inc. Security E...

  • Page 19: Read/Write Access To Sub-Link Master Register

    Write command indicator Access from 2-wire serial interface Master NACK Access from 2-wire serial interface Slave Repeated start condition Figure 8. 2-wire serial I/F read to Sub-Link Master register protocol THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 19/56 Copyright©2016 THine Electronics, Inc. Security E...

  • Page 20: Read/Write Access To Sub-Link Slave Register

    *1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to Sub-Link Slave or remote side 2-wire serial slave is completed. *2 When 2WIRE_MODE = 00 (Clock Stretching Mode) *3 When 2WIRE_MODE = 01 (No Clock Stretching Mode) THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 20/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 21 *1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to Sub-Link Slave or remote side 2-wire serial slave is completed. *2 When 2WIRE_MODE = 00 (Clock Stretching Mode) *3 When 2WIRE_MODE = 01 (No Clock Stretching Mode) THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 21/56 Copyright©2016 THine Electronics, Inc. Security E...

  • Page 22: Read/Write Access To Remote Side 2-Wire Serial Slave Devices Connected To Sub-Link Slave Device

    *1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to Sub-Link Slave or remote side 2-wire serial slave is completed. *2 When 2WIRE_MODE = 00 (Clock Stretching Mode) *3 When 2WIRE_MODE = 01 (No Clock Stretching Mode) THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 22/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 23 *1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to Sub-Link Slave or remote side 2-wire serial slave is completed. *2 When 2WIRE_MODE = 00 (Clock Stretching Mode) *3 When 2WIRE_MODE = 01 (No Clock Stretching Mode) THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 23/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 24 *1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to Sub-Link Slave or remote side 2-wire serial slave is completed. *2 When 2WIRE_MODE = 00 (Clock Stretching Mode) *3 When 2WIRE_MODE = 01 (No Clock Stretching Mode) THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 24/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 25 *1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to Sub-Link Slave or remote side 2-wire serial slave is completed. *2 When 2WIRE_MODE = 00 (Clock Stretching Mode) *3 When 2WIRE_MODE = 01 (No Clock Stretching Mode) THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 25/56 Copyright©2016 THine Electronics, Inc. Security E...

  • Page 26: Gpio

    0xC2 GPIOn_OUT (n=4,3) Pull-up for Open Drain 0x43 GPIO_IO_SEL 0xC3 GPIO_IO_SEL Output (*1) (*1) (default) 0x46 GPIOn_OUTBUF_SEL (n=4,3) GPIOn_OUTBUF_SEL (n=4,3) 0xC6 *1 See Table 27 Figure 11. Through GPIO THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 26/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 27 GPIO IO Direction Number (I:Input, O:Output, -:Unavailable) Master/Slave Address Value Address Value Input Output GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 (HEX) (BIN) (HEX) (BIN) XXX11XXX XXX10XXX Master 0x40 XXX00XXX 0x43 XXX00XXX THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 27/56 Copyright©2016 THine Electronics, Inc. Security E...

  • Page 28: Interruption

    Interrupt Interrupt source source GPIO GPIO Interrupt Interrupt source source Figure 13. 2-wire serial I/F Interrupt to HOST access configuration Table 30. Interrupt output State Interrupt occurred Steady state THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 28/56 Copyright©2016 THine Electronics, Inc. Security E...

  • Page 29: Register Map

    Sub-Link Slave (2-wire serial master) is connected to external 2-wire serial slave devices. Sub-Link Master device has address 0x00-0x7F, Sub-Link Slave device has address 0x80-0xFF. See Figure 14. Figure 14. Sub-Link Master/Slave device Register Address configuration THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 29/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 30 1: "SLINK_TIMEOUT_INT" is allowed to take action on INT output These registers are always active independent of Interrupt permission register. When No clock stretching mode, the value is 1 fixed, otherwise 0 fixed THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 30/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 31 0x2C RD_START_16B 2-wire serial I/F Read Access Start Trigger for 16bit Register Address device 0x2D-0x3F 0x00 Reserved Assignment of 2-wire serial slave device address connected to Sub-Link Slave outside THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 31/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 32 Reserved. Must be 0 0x00 Reserved 0x8F Reserved 0x90 0x00 Reserved -0xBF Interrupt signal from Sub-Link Slave is reported to Sub-Link Master as Cause of interrupt Sub-Link Slave Side (0x02 bit4 SLAVESIDE_INT). THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 32/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 33 Active only when GPIO type is set as "Programmable GPIO" and set as output port. Filter eliminates input glitch shorter than t GPIO input transition is counted as GPIO_INT(0x82 bit3). THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 33/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 34 0xFC Reserved 0xXX PLL_SET2 SSCG PLL setting (*3) 0xFD-0xFF 0xXX Reserved. Must be default setting. See Table 4 SSEN=1 and SPREAD=0 setting is forbidden See Table 8, Table 16 THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 34/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 35 Default value depends on RXDEFSEL setting when Power on sequence. RXDEFSEL=1 → default value is 0 , RXDEFSEL=0 → default value is 1. Filter eliminates input glitch shorter than t GPIO input transition is counted as GPIO_INT(0x02 bit3). THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 35/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 36 0: GPIO1 is open-drain output 1: GPIO1 is push pull output GPIO0 output buffer select GPIO0_OUTBUF_SEL 0: GPIO0 is open-drain output 1: GPIO0 is push pull output 0x47 0x00 Reserved -0x4F THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 36/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 37 SSEN=1 and SPREAD=0 setting is forbidden Described value is typical value. It has variation in the range from min spec value to max spec value of t See Table 8, Table 16 THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 37/56 Copyright©2016 THine Electronics, Inc. Security E...

  • Page 38: Absolute Maximum Ratings

    Input Leak Current High I,IL VIN=VDD Input Leak Current Low I,IL VIN=0V Output Leak Current High in IOZH O,B,BO VIN=VDD Hi-Z State Output Leak Current Low in IOZL O,B,BO VIN=0V Hi-Z State THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 38/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 39 Bi-Directional Buffer RTERM Termination Resistance Receiver State Ω Bi-Directional Buffer VBOD RDIFF=400Ω Differential Output Voltage Bi-Directional Buffer VBOC VDD-0.3 Common Output Voltage Bi-Directional Buffer TRI-STATE PDN=0(THCV231) IBOZ Current PDN1=0(THCV236) THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 39/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 40 PDN Low to CML Output High tTPLL1 Fix Delay LOCKN High to Training Pattern tTNP0 Output Delay LOCKN Low to Data Pattern tTNP1 Output Delay *1 MAINMODE and HFSEL are registers. THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 40/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 41 Bi-Directional Buffer Unit Interval Bi-Directional Buffer tBRF 1000 Rise and Fall Time(20%-80%) Bi-Directional Buffer tBPJTX Transmitter Period Jitter Accuracy (peak to peak) Bi-Directional Buffer tBPJRX Receiver Period Jitter Tolerance (peak to peak) THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 41/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 42 Remote side Stop Condition generating to Read access completion time Depending on characteristics of 2-wire Sub-Link Slave External processing time serial slave devices connected to SSEP Sub-Link Slave THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 42/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 43 Sub-Link Master interrupt valid Sub-Link Master interrupt reset delay Sub-Link Slave interrupt valid 2WIRE_MODE=00 Sub-Link Slave interrupt reset delay 2WIRE_MODE=01 Programmable GPIO input data setup 10000×(1/f Programmable GPIO input data hold THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 43/56 Copyright©2016 THine Electronics, Inc. Security E...

  • Page 44: Ac Timing Diagrams And Test Circuits

    (RF=0) (RF=0) tRCL tRCH (RF=1) (RF=1) RF=0 CLKOUT VDD/2 VDD/2 VDD/2 RF=1 D11-D0 VDD/2 VDD/2 HSYNC,VSYNC tDOUT Figure 16. LVCMOS Output Switching Timing Diagrams THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 44/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 45 Figure 17. CML Output Switching Characteristics THCV231 THCV236 CAPINA C=75~ C=75~ 50Ω 50Ω 200nF 200nF CML Receiver Zdiff=100Ω 50Ω 50Ω Transmitter Vbias Figure 18. CML Buffer Equivalent Circuit THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 45/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 46 Figure 19. Bi-directional CML VBOD/VBOC Test Circuit 100nF 200Ω xCMP 100nF 200Ω xCMN Vdiff = (xCMP) - (xCMN) X=T,R tBRF tBRF Figure 20. Bi-directional CML Switching Timing Diagram and Test Circuit THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 46/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 47 1st bit Figure 21. THCV231 Latency pixel 1st bit tRBIT Vdiff = (RXP) - (RXN) tRCP tRDC RF=0 CLKOUT VDD/2 RF=1 D11-D0 VDD/2 VDD/2 HSYNC,VSYNC Figure 22. THCV236 Latency THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 47/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 48 (N=1,2,4,8) (*1) D11-D0 Data InValid Data HSYNC,VSYNC *1 N depends on setting of OUTSEL_SETTING register (0x6D bit1,0). See Register Map (Table 36) Figure 24. THCV236 Lock/Unlock Sequence THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 48/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 49 Access completion Read access start to Stop Sub-Link Slave’s register Condition Write 1 to 0x26 (SDA) (SCL) Interruption RSSR Figure 27. Read access completion time to Sub-Link Slave register THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 49/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 50 Access completion Stop 2-wire serial slave’s register Condition Write 1 to 0x26 or 0x2C (SDA) (SCL) Interruption Figure 29. Read access completion time to Remote side 2-wire serial slave register THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 50/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 51 Write GPIO output data of Sub-Link Slave to 0xC2 Write 1 to 0x25 (Data_A) (SDA) GPIO Output port Data_A (GPIO4-GPIO3) Figure 33. Programmable GPIO output timing at Sub-Link Slave side THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 51/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 52 (Sub-Link Slave side) Internal Interrupt Event (Sub-Link Slave side) INT of Sub-Link Master Figure 35. GPIO input and other interrupt event timing at Sub-Link Slave side (No Clock Stretching Mode) THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 52/56 Copyright©2016 THine Electronics, Inc. Security E...

  • Page 53: Pcb Layout Guideline Regarding Vdd And Avdd For Thcv236

    AVDD/VDD pins (Bad Example). Good Example 1 Good Example 2 3.6V-1.7V Bottom Layer Through-hole ferrite bead bypass Close to power pin capasitor as possible Example Bad Example THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 53/56 Copyright©2016 THine Electronics, Inc. Security E...

  • Page 54: Package

    Package TOP VIEW LASER MARK FOR PIN1 5.00 BOTTOM VIEW 3.65 0.25 0.50 0.40 SIDE VIEW Unit : mm Figure 36. 32-pin QFN package physical dimension THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 54/56 Copyright©2016 THine Electronics, Inc. Security E...
  • Page 55 TOP VIEW LASER MARK FOR PIN1 9.00 BOTTOM VIEW 7.20 0.25 0.50 0.40 SIDE VIEW Unit : mm Figure 37. 64-pin QFN package physical dimension THCV231_THCV236_Rev.2.30_E THine Electronics, Inc. 55/56 Copyright©2016 THine Electronics, Inc. Security E...

  • Page 56: Notices And Requests

    Specified Product for it not conforming to the aforementioned demands and specifications. 5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent that the user and THine have been previously and explicitly agreed to each other.

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