THine THCS251 Instruction Manual

35-bits gpio or high speed bus signal transceiver

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THCS251_Rev.3.01_E
General description
The THCS251 integrates Serializer and Deserializer
onto a single chip, which supports general purpose
input and output (GPIO) signals through two pairs of
differential signal.
GPIO sampling clock is selectable from external
reference clock or internal oscillator clock.
The 8B10B encoding and decoding adopted by
THCS251 is easy to connect to optical / wireless
communication devices with high robustness and DC
balanced signal.
The built-in adaptive equalizer enables flexible cable
selection.

Application

The THCS251 can applicable to any systems which
have many control signals between PCBs, for
example Multi-function printers, Amusement
machines, Factory Automation and TVs.

Block diagram

THCS251 (Master mode)
REFEN
OSC
REFIN
GPIO
D0/D34
...
D34/D0
LDO
Copyright©2023 THine Electronics, Inc.
THCS251
35-bits GPIO or high speed Bus signal Transceiver
SSCG
PLL

Features

Support up to 35-bits GPIO
Not required to input GPIO sampling clock in
internal oscillator clock mode
Full duplex communication by two pairs of
differential signal
Output buffer open-drain or push-pull selectable
Support up to 8-bits low speed GPIO in low
power Standby mode
Integrated adaptive equalizer for long or lossy
media
8B10B encoding and decoding
Configurable digital noise filter
Error detection and indication
External reference clock frequency: 9-100MHz
Spread Spectrum Clock Generator to reduce EMI
Operating single power supply voltage: 1.7 V -
3.6 V
Wide range IO voltage: 1.7V - 3.6V
Operating ambient temperature: -40°C to 85°C
TXP
RXP
TXN
RXN
TXN
RXN
TXP
RXP
1/33
THCS251 (Slave mode)
LDO
PLL
SSCG
OSC
THine Electronics, Inc.
GPIO
D34/D0
...
D0/D34
REFOUT
SC: E

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Summary of Contents for THine THCS251

  • Page 1: Contents Page General Description

    Standby mode  Integrated adaptive equalizer for long or lossy The 8B10B encoding and decoding adopted by media THCS251 is easy to connect to optical / wireless  8B10B encoding and decoding communication devices with high robustness and DC ...
  • Page 2: Table Of Contents

    7.6.2. Spread Spectrum Clock Generator (SSCG) and REFIN frequency..........28 7.7. Error detection and indication ....................... 29 7.8. Standby mode ............................30 Package ................................31 Notices and Requests ............................. 32 Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 2/33 SC: E...
  • Page 3: Pin Configuration

    D17 / D17 D16 / D18 CAPINP D15 / D19 INT / LOCKN D14 / D20 TEST1 D13 / D21 RESETN D12 / D22 RESERVED D11 / D23 FILTSEL1 D10 / D24 Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 3/33 SC: E...
  • Page 4: Pin Description

    DATA_WIDTH select Table 14 Table 11 RF:(Master mode) input clock edge select Figure 14 RF:(Slave mode) output clock edge select OSCSEL0 OSCSEL0: (Master mode) Oscillator clock frequency select Table 10 Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 4/33 SC: E...
  • Page 5 D15(Slave mode): Data input/output D20/ D20(Master mode): Data input/output D14(Slave mode): Data input/output D21/ D21(Master mode): Data input/output D13(Slave mode): Data input/output D22(Master mode): Data input/output D22/ D12(Slave mode): Data input/output Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 5/33 SC: E...
  • Page 6 TEST1 TEST1 shall be tied to Ground. TEST2 TEST2 shall be tied to Ground. Decoupling capacitor Pin, 1.2V output. Figure 9 CAPOUT 1.2V Analog power supply input. Figure 9 CAPINA Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 6/33 SC: E...
  • Page 7 BO : Open-drain LVCMOS Bi-directional buffer BL : Low speed 5V tolerant schmitt trigger LVCMOS Bi-directional buffer BT : Low speed LVCMOS Bi-directional buffer 5V tolerant Power/Ground PWR : Power supply GND : Ground Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 7/33 SC: E...
  • Page 8: Absolute Maximum Ratings

    *1: Thermal parameters are not guaranteed value. This value assists board and system level designers. Recommended operating conditions Parameter Unit Supply voltage(VDD,AVDD) Operating ambient temperature °C VDD and AVDD supply voltage shall be the same voltage. Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 8/33 SC: E...
  • Page 9: Electrical Characteristics

    PWR : Power supply *1: Master mode of Unidirectional transmission mode, 35-bits GPIO input, 80MHz of REFIN clock *2: Slave mode of Unidirectional transmission mode, 35-bits GPIO output, 80MHz of REFOUT clock Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 9/33...
  • Page 10: Lvcmos/Analog Input Dc Specifications

    B : LVCMOS Bi-directional buffer BO : Open-drain LVCMOS Bi-directional buffer BL : Low speed 5V tolerant schmitt trigger LVCMOS Bi-directional buffer BT : Low speed 5V tolerant LVCMOS Bi-directional buffer Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 10/33 SC: E...
  • Page 11: Lvcmos Ac Characteristics

    FILTSEL0=0 Input data to output data FILTSEL1=0 19 tDCP 35 tDCP tRCD delay (Slave mode to Master FILTSEL0=1 mode) FILTSEL1=1 24 tDCP 43 tDCP FILTSEL0=0 FILTSEL1=1 34 tDCP 59 tDCP Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 11/33 SC: E...
  • Page 12 (RF=0) (RF=0) tTCL tTCH (RF=1) (RF=1) RF=0 REFIN VDD/2 VDD/2 VDD/2 RF=1 D0-D34 VDD/2 VDD/2 Figure 1 LVCMOS input timing diagram = 10Ω Test Point = 8pF Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 12/33 SC: E...
  • Page 13 DATA2 DATA3 D34-D0 tTCD Chip Slave mode Inputs DATA1 DATA2 DATA3 D34-D0 Chip Master mode Outputs DATA1 DATA2 DATA3 D0-D34 tRCD Figure 3 GPIO Input to Output delay timing diagram Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 13/33 SC: E...
  • Page 14: Cml Dc Characteristics

    Input unit interval 2222 Training pattern input to LOCKN low tRPLL0 Unidirectional mode delay tRPLL1 RESETN low to LOCKN High delay Unidirectional mode tRLCK0 LOCKN low to data output delay Unidirectional mode Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 14/33 SC: E...
  • Page 15 Figure 4 CML output AC characteristics diagram THCS251 THCS251 CAPINP C=75~ C=75~ 50Ω 50Ω 200nF 200nF CML Receiver Zdiff=100ohm 50Ω 50Ω CML Transmitter Vbias Figure 5 CML buffer equivalent circuit Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 15/33 SC: E...
  • Page 16 Valid Output Invalid Valid D17/D17s Training Normal tRRDY READYs D18/D16s Invalid Input Invalid Input Valid Invalid Input Valid Input D34/D0s Figure 6 GPIO/CML Bi-directional mode Power on & Reset timing diagram Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 16/33 SC: E...
  • Page 17 Invalid Clock Invalid Clock Invalid Clock Dashed line : RF=1 Hi-Z Hi-Z D34/D0s Invalid Invalid Output Valid Output Valid Output Figure 7 GPIO/CML Unidirectional mode lock & unlock timing diagram Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 17/33 SC: E...
  • Page 18 Standby mode Normal mode Standby mode operation operation operation GPIO Slave Normal mode Normal mode Standby mode Standby mode Hi-Z operation operation operation GPIO Figure 8 Standby mode timing diagram Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 18/33 SC: E...
  • Page 19: Cml Line Eye Diagrams

    THCS251_Rev.3.01_E CML Line Eye diagrams 6.1. CML output Eye diagrams 1UI=1/(serial data rate) Y=0mV X=0 UI X=1 UI X[UI] Y[mV] 0.15 0.355 0.645 0.85 0.645 -175 -175 0.355 -140 Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 19/33 SC: E...
  • Page 20: Cml Input Eye Diagrams

    THCS251_Rev.3.01_E 6.2. CML input Eye diagrams 1UI=1/(serial data rate) Y=0mV X=0 UI X=1 UI X[UI] Y[mV] 0.25 0.75 Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 20/33 SC: E...
  • Page 21: Function

    GPIO signal in low power Standby mode. It does not require any external clock generators e.g. a crystal oscillator. A pair of THCS251 enables to monitor and control peripheral devices via GPIOs. In case communication errors occur, they keep the GPIO signals and report by an interrupt signal.
  • Page 22: Transmission Mode

    Full duplex Bi-directional transmission mode THCS251 can be used a pair of Master mode and Slave mode. Master mode samples data by external reference clock or internal oscillator clock. Slave mode samples data by CDR (Clock Data Recovery) clock generated by Rx.
  • Page 23 “=>” means Downstream (GPIO input in Master mode and GPIO output in Slave mode). “<=” means Upstream (GPIO input in Slave mode and GPIO output in Master mode). Start communication after setting each "Use case" in both Master/Slave. Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 23/33...
  • Page 24: Unidirectional Transmission Mode

    7.4.2. Unidirectional transmission mode THCS251 operates in Unidirectional transmission mode by setting DIRSEL1=1 and DIRSEL0=1. A pair of differential signal from Slave mode to Master mode shall not be connected. LOCKN connection from Slave mode to Master mode is required.
  • Page 25: Io Configuration

    Input and Output digital noise filter THCS251 has digital noise filters for GPIO input (for CMOS input noise immunity) and output (for CML Line noise immunity) which are configured by setting FILTSEL1 and FILTSEL0 shown in Table 5 and Table 6. The data width less than (tap_num - 1) tFLTCK is filtered.
  • Page 26: Sampling Clock Configuration

    Sampling Description REFEN MSSEL OSCSEL1 OSCSEL0 DATA_ DATA_ frequency WIDTH=0 WIDTH=1 [*1] 20MHz 600Mbps 1Gbps Prohibition (Master 40MHz 1.2Gbps 2.0Gbps mode) 80MHz 2.4Gbps Prohibition *1 Typical value, Spec is typical±20% Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 26/33 SC: E...
  • Page 27 Description REFIN sampling edge REFOUT output edge Fall edge Fall edge Rise edge Rise edge Data Data REFIN REFOUT RF=1 RF=1 RF=0 RF=0 Figure 14 Input / Output clock edge Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 27/33 SC: E...
  • Page 28: Spread Spectrum Clock Generator (Sscg) And Refin Frequency

    Spread Spectrum Clock Generator (SSCG) and REFIN frequency THCS251 CML serial data output, GPIO data output and clock output are modulated by integrated SSCG. Only Master mode operates SSCG function. The SSCG is enabled by setting SSEN. When SSCG is enabled and operated with an external REF clock, RESET should be released after the input clock has stabilized.
  • Page 29: Error Detection And Indication

    THCS251_Rev.3.01_E 7.7. Error detection and indication THCS251 has READY and INT for indicating Link status of CML Line communication. READY indicates establishment of communication for GPIOs. INT indicates CML Link communication error. Table 15 READY and INT Status Description READY...
  • Page 30: Standby Mode

    7.8. Standby mode THCS251 operates in Standby mode by setting STANDBY=1. The Standby mode is low power consumption and low frequency sampling rate transmission mode. In Standby mode, THCS251 can transmit up to 8-bits GPIO through handshake communication between Master mode and Slave mode. Polling period is 100ms.
  • Page 31: Package

    LASER MARK FOR PIN1 9.00 BOTTOM VIEW 1.10 6.00 0.09 R PIN1 ID 0.20 R 0.25 0.50 0.40 SIDE VIEW Figure 15 64-pin QFN package physical dimension Unit : mm Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 31/33 SC: E...
  • Page 32: Notices And Requests

    THine Electronics, Inc. (“THine”) is not responsible for possible errors and omissions in this material. Please note even if errors or omissions should be found in this material, THine may not be able to correct them immediately.
  • Page 33 THine or THine’s licensor. The user must enter into a license agreement with THine or THine’s licensor to be granted of such license or right.

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