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THine THCS252 Instruction Manual

THine THCS252 Instruction Manual

20-bits gpio or high speed bus signal transceiver

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THCS252_Rev.2.01_E
General description
The THCS252 integrates Serializer and Deserializer
onto a single chip, which supports general purpose
input and output (GPIO) signals through two pairs of
differential signal.
GPIO sampling clock is selectable from external
reference clock or internal oscillator clock.
The 8B10B encoding and decoding adopted by
THCS252 is easy to connect to optical / wireless
communication devices with high robustness and DC
balanced signal.
The built-in adaptive equalizer enables flexible cable
selection.
Application
The THCS252 can applicable to any systems which
have many control signals between PCBs, for
example Multi-function printers, Amusement
machines, Factory Automation and TVs.
Block diagram
THCS252 (Master mode)
REFEN
OSC
REFIN
GPIO
D0/D19
...
D19/D0
Copyright©2023 THine Electronics, Inc.
THCS252
20-bits GPIO or high speed Bus signal Transceiver
SSCG
PLL
TXP
TXN
LDO
1/31
Features
Support up to 20-bits GPIO
Not required to input GPIO sampling clock in
internal oscillator clock mode
Full duplex communication by two pairs of
differential signal
Output buffer open-drain or push-pull selectable
Support up to 8-bits low speed GPIO in low
power Standby mode
Integrated adaptive equalizer for long or lossy
media
8B10B encoding and decoding
Configurable digital noise filter
Error detection and indication
External reference clock frequency:
15-100MHz
Spread Spectrum Clock Generator to reduce EMI
Operating single power supply voltage: 1.7 V -
3.6 V
Wide range IO voltage: 1.7V - 3.6V
Operating ambient temperature: -40°C to 85°C
THCS252 (Slave mode)
RXP
RXN
TXN
RXN
TXP
RXP
PLL
LDO
GPIO
D19/D0
...
D0/D19
REFOUT
SSCG
OSC
THine Electronics, Inc.
SC: E

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Summary of Contents for THine THCS252

  • Page 1 Standby mode  Integrated adaptive equalizer for long or lossy The 8B10B encoding and decoding adopted by media THCS252 is easy to connect to optical / wireless  8B10B encoding and decoding communication devices with high robustness and DC ...
  • Page 2 7.6.2. Spread Spectrum Clock Generator (SSCG) and REFIN frequency..........26 7.7. Error detection and indication ....................... 27 7.8. Standby mode ............................28 Package ................................29 Notices and Requests ............................. 30 Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 2/31 SC: E...
  • Page 3 REFIN / REFOUT/ OSCSEL1 (TOP VIEW) CAPINA 49EXPGND D10 / D9 D9 / D10 CAPINP D8 / D11 INT / LOCKN D7 / D12 TEST1 D6 / D13 RESETN D5 / D14 Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 3/31 SC: E...
  • Page 4 RF: (Slave mode) output clock edge select OSCSEL0:(Master mode) Oscillator clock Table 9 OSCSEL0 frequency select OSCSEL0: (Slave mode) Set to Low D0(Master mode): Data input D19(Slave mode): Data output Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 4/31 SC: E...
  • Page 5 1: SSCG PLL is enabled SSEN(Slave mode): Set to Low Table 5 FILTSEL0 FILTSEL0: digital noise filter select INT: Interrupt output when READY=1 INT/ 0: Error occurred LOCKN 1(pull-up): No Error Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 5/31 SC: E...
  • Page 6 BO : Open-drain LVCMOS Bi-directional buffer BL : Low speed 5V tolerant schmitt trigger LVCMOS Bi-directional buffer BT : Low speed LVCMOS Bi-directional buffer 5V tolerant Power/Ground PWR : Power supply GND : Ground Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 6/31 SC: E...
  • Page 7 *1: Thermal parameters are not guaranteed value. This value assists board and system level designers 4. Recommended operating conditions Parameter Unit Supply voltage(VDD,AVDD) Operating ambient temperature °C VDD and AVDD supply voltage shall be the same voltage. Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 7/31 SC: E...
  • Page 8: Electrical Characteristics

    PWR : Power supply *1: Master mode of Unidirectional transmission mode, 20-bits GPIO input, 100MHz of REFIN clock *2: Slave mode of Unidirectional transmission mode, 20-bits GPIO output, 100MHz of REFOUT clock Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 8/31...
  • Page 9 B : LVCMOS Bi-directional buffer BO : Open-drain LVCMOS Bi-directional buffer BL : Low speed 5V tolerant schmitt trigger LVCMOS Bi-directional buffer BT : Low speed 5V tolerant LVCMOS Bi-directional buffer Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 9/31 SC: E...
  • Page 10 19 tDCP 35 tDCP FILTSEL0=1 tRCD delay (Slave mode FILTSEL1=1 Master mode) 24 tDCP 43 tDCP FILTSEL0=0 FILTSEL1=1 34 tDCP 59 tDCP FILTSEL0=1 RESETN high to READY tRRDY high delay Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 10/31 SC: E...
  • Page 11 Data(Pin type=BT) tTCIP tTCH tTCL (RF=0) (RF=0) tTCL tTCH (RF=1) (RF=1) RF=0 REFIN VDD/2 VDD/2 VDD/2 RF=1 D0-D19 VDD/2 VDD/2 Figure 1 LVCMOS input timing diagram Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 11/31 SC: E...
  • Page 12 DATA2 DATA3 D19-D0 tTCD Chip Slave mode Inputs DATA1 DATA2 DATA3 D19-D0 Chip Master mode Outputs DATA1 DATA2 DATA3 D0-D19 tRCD Figure 3 GPIO Input to Output delay timing diagram Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 12/31 SC: E...
  • Page 13 Input unit interval 2222 Training pattern input to LOCKN low tRPLL0 Unidirectional mode delay tRPLL1 RESETN low to LOCKN High delay Unidirectional mode tRLCK0 LOCKN low to data output delay Unidirectional mode Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 13/31 SC: E...
  • Page 14 Figure 4 CML output AC characteristics diagram THCS252 THCS252 CAPINP C=75 ~ C=75 ~ 50Ω 50Ω 200nF 200nF CML Receiver Zdiff=100ohm 50Ω 50Ω CML Transmitter Vbias Figure 5 CML buffer equivalent circuit Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 14/31 SC: E...
  • Page 15 Valid Output Invalid Valid D10/D9s Training Normal tRRDY READYs D9/D10s Invalid Input Invalid Input Valid Invalid Input Valid Input D19/D0s Figure 6 GPIO/CML Bi-directional mode Power on & Reset timing diagram Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 15/31 SC: E...
  • Page 16 Invalid Clock Invalid Clock Invalid Clock Dashed line : RF=1 Hi-Z Hi-Z D19/D0s Invalid Invalid Output Valid Output Valid Output Figure 7 GPIO/CML Unidirectional mode lock & unlock timing diagram Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 16/31 SC: E...
  • Page 17 THCS252_Rev.2.01_E Figure 8 Standby mode timing diagram Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 17/31 SC: E...
  • Page 18 THCS252_Rev.2.01_E 6. CML Line Eye diagrams 6.1. CML output Eye diagrams 1UI=1/(serial data rate) Y=0mV X=0 UI X=1 UI X[UI] Y[mV] 0.15 0.355 0.645 0.85 0.645 -175 -175 0.355 -140 Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 18/31 SC: E...
  • Page 19 THCS252_Rev.2.01_E 6.2. CML input Eye diagrams 1UI=1/(serial data rate) Y=0mV X=0 UI X=1 UI X[UI] Y[mV] 0.25 0.75 Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 19/31 SC: E...
  • Page 20 GPIO signal in low power Standby mode. It does not require any external clock generators e.g. a crystal oscillator. A pair of THCS252 enables to monitor and control peripheral devices via GPIOs. In case communication errors occur, they keep the GPIO signals and report by an interrupt signal.
  • Page 21 Full duplex Bi-directional transmission mode THCS252 can be used a pair of Master mode and Slave mode. Master mode samples data by external reference clock or internal oscillator clock. Slave mode samples data by CDR (Clock Data Recovery) clock generated by Rx.
  • Page 22 7.4.2. Unidirectional transmission mode THCS252 operates in Unidirectional transmission mode by setting DIRSEL1=1 and DIRSEL0=1. A pair of differential signal from Slave mode to Master mode shall not be connected. LOCKN connection from Slave mode to Master mode is required.
  • Page 23 Input and Output digital noise filter THCS252 has digital noise filters for GPIO input (for CMOS input noise immunity) and output (for CML Line noise immunity) which are configured by setting FILTSEL1 and FILTSEL0 shown in Table 5 and Table 6. The data width less than (tap_num - 1) tFLTCK is filtered.
  • Page 24 Table 9 Oscillator Clock Frequency and CML Line data rate Setting Sampling CML Line data Description REFEN MSSEL OSCSEL1 OSCSEL0 frequency [*1] rate [*1] 20MHz 600Mbps Prohibition (Master 40MHz 1.2Gbps mode) 80MHz 2.4Gbps *1 Typical value, Spec is typical±20% Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 24/31 SC: E...
  • Page 25 Description REFIN sampling edge REFOUT output edge Fall edge Fall edge Rise edge Rise edge Data Data REFIN REFOUT RF=1 RF=1 RF=0 RF=0 Figure 14 Input / Output clock edge Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 25/31 SC: E...
  • Page 26 7.7. Spread Spectrum Clock Generator (SSCG) and REFIN frequency THCS252 CML serial data output, GPIO data output and clock output are modulated by integrated SSCG. Only Master mode operates SSCG function. The SSCG is enabled by setting SSEN. When SSCG is enabled and operated with an external REF clock, RESET should be released after the input clock has stabilized.
  • Page 27 THCS252_Rev.2.01_E 7.8. Error detection and indication THCS252 has READY and INT for indicating Link status of CML Line communication. READY indicates establishment of communication for GPIOs. INT indicates CML Link communication error. Table 14 READY and INT Status Description READY...
  • Page 28: Standby Mode

    THCS252_Rev.2.01_E 7.9. Standby mode THCS252 operates in Standby mode by setting STANDBY =1. The Standby mode is low power consumption and low frequency sampling rate transmission mode. In Standby mode, THCS252 can transmit up to 8-bits GPIO through handshake communication between Master mode and Slave mode. Polling period is 100ms.
  • Page 29: Top View

    7.00 LASAR MARK FOR PIN1 BOTTOM VIEW 4.03 1.085 0.125 R PIN1 ID 0.20 R 0.50 0.40 0.25 SIDE VIEW Figure 15 48-pin QFN package physical dimension Unit : mm Copyright©2023 THine Electronics, Inc. THine Electronics, Inc. 29/31 SC: E...
  • Page 30 THine Electronics, Inc. (“THine”) is not responsible for possible errors and omissions in this material. Please note even if errors or omissions should be found in this material, THine may not be able to correct them immediately.
  • Page 31 THine or THine’s licensor. The user must enter into a license agreement with THine or THine’s licensor to be granted of such license or right.