Panasonic TDA 100 Service Manual page 27

Signal Name
nBACK Bus Acknowledge: This indicates Bus Acknowledge.
nBATT This indicates whether external battery is connected or not.L: Connected
nBAT_ALM Battery Alarm Signal: This indicates the declined voltage of lithium battery. (L: Alarm condition)
nBREQ Bus Request: Bus request signal
nBS Bus Cycle Start: Bus cycle start signal
nCASL Lower Byte Address Column Address Strobe: CAS signal for SDRAM
nCASU Upper Byte Address Column Address Strobe: CAS signal for SDRAM
CH_SEL[0] Synchronous Signal for CODEC (For MOH#1/Page#1)
CH_SEL[1] Synchronous Signal for CODEC (For MOH#2/Page#2)
CH_SEL[2] Synchronous Signal for CODEC (For RMT)
CKE Clock Enable: CKE signal for SDRAM
CKIO Clock I/O Terminal: For bus clock of SDRAM (IC305, IC306) and ASIC (IC101) CPU (IC100) outputs the clock of four
times frequency as many as Source clock (16.384MHz).
nCS0 Chip Select 0: Chip select signal for flash memory
nCS2 Chip Select 2: Chip select signal for the expanded SDRAM (Future Option, Reserve at present.)
nCS3 Chip Select 3: Chip select signal for SDRAM
nCS4 Chip Select 4: Chip select signal for SRAM
nCS5 Chip Select 5: Chip select signal for ASIC
nCS6 Chip Select 6: Chip select signal for USB I/F and SD card I/F
nCS_FLASH0 Chip Select for Flash memory0: CS signal for IC303
nCS_FLASH1 Chip Select for Flash memory1: CS signal for IC304 (reserve)
nCS_SDB0 Chip Select for Sd card I/F
nCS_SDB1 Reserve
nCS_SRAM0 Chip Select for SRAM0: CS signal for IC301
nCS_SRAM1 Chip Select for SRAM1: CS signal for IC302
nCS_USB Chip Select for USB I/F
nCTS2 Clear To Send from RS-232C connector
CTS_RMT Clear to Send: Flow signal for modem
CT_C8 Clock8.192MHz clock outputted from PLL master
CT_D[0] -[7] CT Data Bus: Two-way serial data bus to which the drive from any card is possible in the system.
CT_FRAME Frame Signal: 8KHz frame signal outputted from the master
CT_NETREF Backup Synchronous Signal (MAX 2MHz) 8KHz signal output from slave etc.
C_CS[0] Chip Select For RMT
D[0] -D[31] Data Bus
nDACK0-1 DMA Acknowledge: For USB I/F
DCD2 Data Carrier Detect
DCLK_RMT Codec Clock (8MHz): For RMT
nDC_ALM DC ALARM:DC alarm signal; Indicates the declined DC voltage. (L: Alarm condition)
DIN_RMT Codec Data Input: For RMT
DOUT_RMT Codec Data Output: For RMT
DQMLL (nWE0) Data Input/Output Mask (Write Enable): DQM signal for SDRAM and WE signal for each memory IC and ASIC
DQMLU (nWE1)
DQMUL (nWE2)
DQMUU (nWE3)
nDREQ0-1 DMA Request: For USB I/F
DSR2 Data Set Ready from RS-232C connector
DSR_RMT Data Set Ready from RS-232C connector
DTR2 Data Terminal Ready to RS-232C connector
EC_AD[0] -[15] Address of EC Synchronous Bus, Data Bus (4MHz)
EC_nCBE[1]-[0] EC Bus Command/Byte Enable: The initiator drives as bus command in the address phase and as byte enable in the
data phase.
EC_nCDET EC Line Card Detection Signal Asynchronous interrupting signal
EC_CLK Clock of EC Synchronous Bus (8MHz) All the EC bus signal except nRESET/EC_INT operates in sync with this
signal.
EC_nFRAME EC Cycle Frame Signal: This indicates the drive by initiator and the execution of ECI bus cycle.
EC_nINT EC Interrupting Signal: This is asserted, when slave interrupt occurs.
EC_PAR Parity Bit of EC Synchronous Bus: Drive by applying even parity to AD[15:0] and CBE[1:0]. (4MHz)
EC_nPERR EC Parity Error: Flag indicating error status by parity flag
EC_nRST EC Reset Input: System reset input signal
EC_nSTOP EC Bus Stop Signal: This is asserted, when target requests transaction halt to initiator.
EC_nTRDY EC Target Ready Signal: This indicates the drive by target and the possible data transfer.
nFAN_ALM Fan Alarm: It goes Low at the error of the L Power Supply's FAN. It goes High when the FAN is normal and, Power
Supply S and M, which does not carry the FAN, are used.
FSEL0 Signal switching the Flash Memory address of the MEX card. FSEL0 is set by hard jumper.L: The number of Flash
Memory chips on the MPR is 1pc. H: The number is 2pcs.
GAIN0-1 Gain: Gain adjustment signal for the RMT card (Reserve)
HALT This alarms the occurrence of the declined DC voltage to line card. H: Active L: Normal
nINIT System Initialization Switch Input: L: At system initialization, H: At normal start-up
Function
27
KX-TDA100CE