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Microchip Technology Microsemi UG0677 User Manual

Microchip Technology Microsemi UG0677 User Manual

Polarfire fpga transceiver
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UG0677
User Guide
PolarFire FPGA Transceiver

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Summary of Contents for Microchip Technology Microsemi UG0677

  • Page 1 UG0677 User Guide PolarFire FPGA Transceiver...
  • Page 2 About Microsemi ©2021 Microsemi, a wholly owned Microsemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of subsidiary of Microchip Technology Inc. All semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets.

  • Page 3: Table Of Contents

    Contents 1 Revision History ........... . . 1 Revision 9.0 .
  • Page 4 4.4.1 Timing Constraints ............101 4.4.2 Physical Constraints .
  • Page 5 Figures Figure 1 Transceiver Lane Overview ............5 Figure 2 Transceiver Receiver .
  • Page 6 Figure 55 PCS Rate Switch between 8b10b and 64b66b Mode ........75 Figure 56 Transceiver Reference Clock Selection from Catalog .
  • Page 7 Tables Table 1 Supported Serial Protocols ............4 Table 2 CDR Lock Mode Values .

  • Page 8: Revision History

    Revision History Revision History The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the current publication. Revision 9.0 The following is a summary of the changes in this revision. •...

  • Page 9: Revision 5.0

    Revision History • Information about new latency was updated. See Table 15, page 53. • Information about Transceiver Data Path Latency, page 53 was added. • Information about footnote was updated. See Table 21, page 68. • Information about PCS Rate Switch Between 8b10b and 64b66b Mode for CPRI, page 75 was added.

  • Page 10: Revision 1.0

    Revision History • Information about Word Alignment was added as sub-section to 8b10b, page 23. See Word Alignment (Byte Boundary or Comma Detect), page 24. • Updated Figure 52, page 71 and Figure 53, page 72. • Information about LANE#_RX_VAL port name description was updated. See Table 4, page 16, Table 7,...

  • Page 11: Overview

    Overview Overview ® The PolarFire FPGA family includes multiple embedded low-power, performance-optimized transceivers. Each transceiver has both the physical medium attachment (PMA), protocol physical coding sub-layer (PCS) logic, and interfaces to the FPGA fabric. The transceiver has a multi-lane architecture with each lane natively supporting serial data transmission rates from 500Mbps (250 Mbps with interpolation) to 12.7 Gbps.

  • Page 12: Figure 1 Transceiver Lane Overview

    Overview Transceiver Lane Overview Figure 1 • PCIe Sub-System (PCIESS) Transmit PMA Transmit PCS XCVR_TXP PCIe/PIPE Pre-/Post- Emphasis 8b10b Encoder Out of Band Serializer Transmit PCS/ 64b/6xb Fabric Electrical Encoder Interface Idle PCIe XCVR_TXN PMA Only ÷ 1, 2, 4, 8, 11 Divider Transmit PLL CDR Far-End...

  • Page 13: Features

    Overview Features The PolarFire transceiver enables users to quickly build high-speed links that support many standard protocols with the features listed: • Supports data rates from 500 Mbps (250 Mbps with interpolation) up to 12.7 Gbps. • Serialization/deserialization width at FPGA fabric interface—8, 10, 16, 20, 32, 40, 64, and 80 bits. •...

  • Page 14: Functional Description

    Functional Description Functional Description The PolarFire transceiver (Figure 1, page 5) is divided into four distinct transmit (Tx) and receive (Rx) blocks: • • PCS interface block, including a dedicated PCIe PCS • Transmit PLL (Tx PLL) • Reference clock inputs The high-speed PMA blocks connect to the FPGA fabric through the PCS block.

  • Page 15: Figure 2 Transceiver Receiver

    Functional Description Transceiver Receiver Figure 2 • Reference Clock Network Receive PMA Receive PCS XCVR_RXP PMA Only Monitor 64b/6xb CDR w/DFE Decoder Receive CTLE Polarity Deserializer PCS/ 8b10b Fabric Decoder Interface Signal PCIe/PIPE XCVR_RXN Detect Divider PCIe Sub-System (PCIESS) 3.1.1.1 Receive Input Buffer The receiver provides an external input interface through differential pins, XCVR_RXP/N, as shown in the following figure.

  • Page 16: Figure 4 Input Signal Path

    Functional Description 3.1.1.2 Loss of Signal Detect (LOS) Loss of signal (LOS) detection is included within the receiver path. The LOS circuitry detects the initial incoming signal determining a valid input (electrical RX_IDLE=0) for clock-data recovery operations. The LOS peak detection captures the most positive and negative points of the input signal and compares the amplitude to a limit set by the user.
  • Page 17 Functional Description 3.1.1.5 Eye Monitor The eye monitor is on-device circuitry to visualize the post-equalization signal quality in the receive path while the data path is still active in the system. The non-destructive eye monitor runs a separate sampler in parallel with the CDR and DFE data sampler. This permits the system to remain operational while the eye monitor is functioning.

  • Page 18: Figure 5 Cdr Lock Mode Options

    Functional Description When BMR mode is selected, LANE_X_CDR_LOCKMODE[1:0] are exposed for CDR mode control. The following table lists the value and the description of the CDR lock mode control bits. CDR Lock Mode Values Table 2 • LANE_X_CDR_LOCKMODE[1:0] Values Mode 2’b00 Not used 2’b01...
  • Page 19 Functional Description 3.1.1.9 Receiver Calibration The PolarFire XCVR receivers include both analog and digital blocks that require calibration to compensate for process, voltage, and temperature (PVT) variations in conjunction with signal integrity. The embedded calibration block of PolarFire transceiver performs calibration operations that optimize the performance of the transceiver interconnection.

  • Page 20: Table 3 Mode Of Operations

    Functional Description DFE can also be set in static mode where the user can specify the exact DFE coefficients required by the design. DFE Coefficients are set through PDC commands (see DFE Coefficients, page 104) can be used from the register rather than from calibration. This mode does not expose the CALIB_REQ pin or any of the pins to trigger auto-calibration or incremental calibration.

  • Page 21: Transmitter

    Functional Description example, JESD204B startups with a continuous K28.5 stream, then later shifts to actual 8b10b data. This is a change in data pattern and may impact calibrated DFE coefficients. The PolarFire transceiver component is generated by the Libero software to include enhanced receiver management logic to control the proper calibration of the receiver, see Enhanced Receiver Management, page 16.

  • Page 22: Figure 7 Transmit Output Driver

    Functional Description 3.1.2.1 Serializer The serializer provides the link between the high-speed interface and the transmit PCS by performing a parallel-to-serial conversion. Each lane has up to 40-bit data bus to the transmit PCS block and a separate post-divider for a divide by 1, 2, 4, 8, or 11. The post dividers are provided to divide the high- speed clock from the TxPLL to exactly what the serializer requires for the data rate.

  • Page 23: Enhanced Receiver Management

    Functional Description Enhanced Receiver Management Enhanced receiver management (ERM) is implemented in FPGA logic inside the XCVR component. The ERM adds DFE/CDR calibration management, and lock-to-data lock detection capabilities of the PF_XCVR. The RTL is autonomously generated by Libero Software. The generated blocks manage the start-up/on-demand CDR/DFE calibration and fine-grain lock detector with a PMA, 8b10b, and 64b6xb modes of the PF_XCVR.

  • Page 24: Figure 8 Enhanced Receiver Management In Xcvr Configurator

    Functional Description ERM Ports Table 4 • Name Direction Description LANE#_LOS Input LANEx_LOS input which may be asserted from an external source such-as optical SFP during no-signal condition as a means of preventing entry to lock- to-data. This input should be used to control application scenarios where the incoming data stream has enough activity to trigger the LANE#_RX_IDLE but lacks enough transitions to lock the RXPLL.

  • Page 25: Figure 9 Calibration Options For Enhanced Receiver Management Operations

    Functional Description Calibration Options for Enhanced Receiver Management Operations Figure 9 • The following receiver calibration options are provided for the ERM operation. • None (CDR): Select if the XCVR is configured as CDR and no CTLE auto-calibration is performed. Static settings are configured by Libero based on data rate and backplane model.

  • Page 26: Figure 11 Dfe Options

    Functional Description The ERM manages the device behavior at first power-up or release from device reset (DEVRSTn). The ERM managed calibration begins after the device complete its initial startup configuration and the assertion of XCVR_INIT_DONE de-asserts the CTRL_ARST_N. This requires a valid serial data stream to be applied to the RXD input pins at the time of de-assertion of the CTRL_ARST_N signal.

  • Page 27: Figure 12 First Lock Calibration Waveform

    Functional Description Figure 12 • First Lock Calibration Waveform Tx Source device powered-up and transmitting Cannot stop transmitting until RX_VAL rises LANE#_RXD[P-N] Glitches on RX_IDLE is expected for incoming traffic > 5Gbps LANE#_RX_IDLE LANE#_LOS CDR Status(Internal) LANE#_CALIBRATING LANE#_RX_READY_CDR Calibration takes control of RxPLLfor short period of time LANE#_RX_READY (Rx Fine Lock)

  • Page 28: Figure 14 Restart After Initialization

    Functional Description The ERM manages the re-establishment of a link after a break or disruption. A restart begins when a valid data stream is re-applied to the receiver inputs. This starts the operation of the ERM to systematically control the CDR to re-initialize the link. As shown in following figure, the ERM properly re- establishes a CDR fine lock after assuring the link is stable.

  • Page 29: Figure 15 On-Demand Calibration Waveform

    Functional Description Figure 15 • On-Demand Calibration Waveform 1- 10 seconds ** Incoming signal must be appropriate for calibration LANE#_RXD[P-N] Glitches on RX_IDLE is expected for incoming traffic > 5Gbps LANE#_RX_IDLE Do Not Care LANE#_LOS CDR Status(Internal) Calibration Done LANE#_CALIBRATING LANE#_RX_READY_CDR LANE#_RX_READY_CDR may toggle during calibration...

  • Page 30: Transceiver Pcs Interface Modes

    Functional Description Transceiver PCS Interface Modes The transceiver PMA connects with the fabric using four PCS interface modes. PMA-PCS gearing is used in conjunction with the interface clock. The TX_CLK and RX_CLK frequency is equal to the FPGA interface based on the data rate/(PMA-PCS width × PCS gearing). The PCS interface instantiates the embedded transceiver and RTL blocks when the user customizes and generates the block.
  • Page 31 Functional Description 3.3.1.1 Word Alignment (Byte Boundary or Comma Detect) The 8b10b PCS block performs the comma code-word detection and alignment operation. The comma character is used by the receive logic to align the incoming data stream into 10-bit words. The alignment comma descriptions (K28.1, K28.5, and K28.7) are defined in section 36.2.4.9 of the IEEE 802.3.2002.

  • Page 32: Figure 16 8B10B Data Path

    Functional Description Figure 16 • 8b10b Data Path TX_DATA[n*8-1:0], TX_K[n-1:0] TXP, TXN Encoder Serializer CONV 4*10 n = 4 TX_CLK divide by 2 div40 n = 8 div80 n is either 4 or 8, depending on configured serial speed FPGA PCS= 8B10B Fabric RX_DATA[n*8-1:0],...

  • Page 33: Table 6 System Registers Affecting 8B10B Data Path

    Functional Description 3.3.1.4 8b10b System Registers There are specific registers used for configuring the 8b10b lane function options in the PolarFire Device Register Map. Other fields are required to properly program the clocks, resets, XCVR, and lane overlay blocks and data path steering. Required system register field setting combinations required for enabling 8b10 lane usage.

  • Page 34: Table 7 8B10B Port List

    Functional Description System Registers Affecting 8b10b Data Path Table 6 • Register Page xls Register Name Field Name Description Required Value pma_lane DES_CLK_CTRL DESMODE[2:0] Selects parallel bus width of Must select the 40-bit deserializer interface. wide bus mode for 8b10b functionality (3'd7).
  • Page 35 Functional Description 8b10b Port List (continued) Table 7 • Port Name Direction Clock Description LANE#_TX_DATA[N:0] Input TX_CLK_[R:G] Encoded user data from the fabric. The send/receive order is low to high byte. LANE#_PCS_ARST_N Input Asynchronous active-low reset for the PCS lane. This reset is responsible for the reset of the 8b10b logic and COMMA word aligner.
  • Page 36 Functional Description 8b10b Port List (continued) Table 7 • Port Name Direction Clock Description LANE#_RX_READY Output Asynchronous Rises when the enhanced receiver management and CDR completes a fine lock detection to the incoming data transitions and the de-serializer is powered-up. If there is no incoming data to the CDR then the RX_READY is low.

  • Page 37: 64B66B/64B67B

    Functional Description 3.3.2 64b66b/64b67b The 64b66b/64b67b (64b6xb) interface modes are used mainly for 10 Gbps-based protocols, 10G base interface over Ethernet (10GBASE-R/KR), common public radio interface (CPRI) rates of 9.830 Gbps, and 40GBASE-R standards. The 64b/66b encoder is used to achieve DC balance and sufficient data transitions for clock recovery.

  • Page 38: Figure 17 64B6Xb Data Path

    Functional Description 64b6xb Transmit Data Path Blocks, Fabric to PMA Order Table 8 • Tx Block Purpose Tx Disparity Implements inversion of 67-bit symbol. Only for use in Interlaken. Tx Gearbox Outputs continuous stream of 32-bits per clock beat to the PMA given an input consisting of 64-bit block symbols, which has cyclic gaps in its active clock beats.

  • Page 39: Table 10 System Registers Affecting 64B6Xb Data Path

    Functional Description 3.3.2.2 64b6xb System Registers There are specific registers used for configuring the 64b6xb lane function options in the PolarFire Device Register Map. Other fields are required to properly program the clocks, resets, XCVR, and lane overlay blocks and data path steering. Required system register field setting combinations required for enabling 64b6xb lane usage.

  • Page 40: Figure 18 64B66B Receive Sequence For 32-Bit Interface

    Functional Description 3.3.2.3 64b66b Receiver The receiver takes 32-bits or 64-bits of data from the PMA's CDR on each clock beat into the gearbox. The gearbox frames the data into 66-bit symbols by searching for valid values on the sync header bits as per IEEE 802.3 Clause 49.

  • Page 41: Figure 20 64B66B Transmit Sequence For 64-Bit Interface

    Functional Description 3.3.2.4 64b66b Transmit In the transmit direction, the encoded 64-bit blocks are applied to PCS data from the fabric along with the sync headers. When the 64-bit symbol is a control block, like Idle, Start or Terminate, then pcs_hdr[1:0]=0b10.

  • Page 42: Figure 22 64B67B Transmit Sequence For 32-Bit Interface

    Functional Description 3.3.2.5 64b67b Transmit In the recommended configuration for 64b67b, encoded and scrambled data is presented from the fabric into TX_DATA along with sync headers on TX_HDR[3:0]. The data from the fabric must conform to the expected sequence of clock beats according to the fabric interface width. Figure 22 •...

  • Page 43: Figure 23 64B67B Receive Sequence For 32-Bit Interface

    Functional Description Figure 23 • 64b67b Receive Sequence For 32-Bit Interface Sequence timing for the 64-bit interface consists of 67 clock beats with dead cycles at beats 22, 44, and The following table lists the port names and description for the 64b66b/64b67b mode of the PCS module. See section 49.2.4 of the for more information.
  • Page 44 Functional Description 64b66b/64b67b Port List (continued) Table 11 • Port Name Direction Clock Description LANE#_TX_ELEC_IDLE Input Asynchronous Transceiver configurator allows pin to be exposed on component. This input forces XCVR_P/N transmit output pad pair to a common-mode voltage. It is used for low-frequency out-of-band signaling, or to signal entry into a low-power state to the link partner.

  • Page 45: Pipe

    Functional Description 64b66b/64b67b Port List (continued) Table 11 • Port Name Direction Clock Description LANE#_RX_READY Output Rises when the enhanced receiver management and CDR completes a fine lock detection to the incoming data transitions and the de-serializer is powered-up. If there is no incoming data to the CDR then the RX_READY is low.

  • Page 46: Table 12 Pipe Port List

    Functional Description The PIPE interface is used by the embedded PCIESS or can be used with a soft PCIe IP in the FPGA fabric. The embedded PCIESS is accessed through a dedicated interface to the PIPE interface mode, which ties the PCIESS to the PIPE without additional fabric logic. All PHY interface signals are synchronous to the PIPE CLOCK.
  • Page 47 Functional Description PIPE Port List (continued) Table 12 • Port Name Direction Clock Description POWERDOWN[1:0] Input TX_CLK_[R:G] These inputs place the transceiver into one of four power states: P0: normal operational mode. P0s: PCLK remains on, but the receiver conserves power;...
  • Page 48 Functional Description PIPE Port List (continued) Table 12 • Port Name Direction Clock Description LANE#_TXELECIDLE Input TX_CLK_[R:G] When this signal is asserted high, it forces the transmitter to the electrical idle state regardless of power states. When this signal is de-asserted, valid data from TXDATA and TXDATAK are transmitted in the P0 state.
  • Page 49 Functional Description PIPE Port List (continued) Table 12 • Port Name Direction Clock Description LANE#_RX_BYPASS_DATA Output Async RX_BYPASS_DATA output is a low-speed bypass of the differential receiver that is used for the receive pads. This is a a low-frequency out-of-band debug signal. LANE#_PHYSTATUS Output RX_CLK_[R:G] Signals that the PHY has completed its setup and is...

  • Page 50: Pipe Interface Compliance Exceptions

    Functional Description In the MPF500 devices, the TX_CLK_R and RX_CLK_R pins of XCVR lanes placed in the PCIESS(Q0) and GPSS1(Q1) quads cannot drive I/Os. Note: LANE# can be 0, 1, 2, and 3. [R:G] naming is generated based on the use of regional or global resources that are selected with Libero.

  • Page 51: Pma Only

    Functional Description The following figure shows how the soft PIPE interface signals behave when the first detection finds a connected receiver. The difference between receiver presence and absence is the value of RxStatus in simulation, but in real silicon, the delay to the PhyStatus pulse can be different. In real silicon, the Receiver-Not-Present response occurs earlier than a Receiver-Present response.

  • Page 52: Figure 27 Pma-Bus Waveform

    Functional Description The PMA interface bypasses any PCS encoding and decoding logic and is used with customized PCS functionality implemented in the FPGA fabric. The fabric-hosted soft-IP can be customer supplied or soft-IP provided through 3rd-party of Microsemi direct cores. The transceiver PMA mode is useful in supporting protocols such as SDI-HD.

  • Page 53: Figure 29 Pma Only Data Path - Less Than Or Equal To 40-Bits

    Functional Description Figure 29 • PMA Only Data Path – Less Than or Equal to 40-bits TX_DATA[N:0] TXP, TXN Serializer 8, 10, N= 8, 10, div8, 16, 20, 16, 20, div10, div16, 32, 40 32, 40 div20, div32, div40 TX_CLK FPGA PCS-PMA Only- Native Fabric...
  • Page 54 Functional Description PMA Port List (continued) Table 13 • Port Name Direction Clock Description LANE#_TX_ELEC_IDLE Input Asynchronous Transceiver configurator allows pin to be exposed on component. This input forces XCVR_P/N transmit output pad pair to a common-mode voltage. This can be used for low-frequency out-of-band signaling, or to signal entry into a low-power state to the link partner.

  • Page 55: Pcs/Fpga Fabric Interface

    Functional Description PMA Port List (continued) Table 13 • Port Name Direction Clock Description LANE#_RX_READY Output Lane#_ RX_READY = 1 means the Rx PLL is locked. LANE#_RX_READY rises when the enhanced receiver management and CDR completes a fine lock detection to the incoming data transitions and the de-serializer is powered-up.

  • Page 56: Non-Deterministic Interface

    Functional Description • Global-Shared: These clocks are similar to Globals but have resources to allow sharing between the TxPLLs. The sharing of lane clocking resources results in equal latency in the transmitter phase compensation FIFO of all shared lanes. Note: Global-Shared mode allows the global clock output from one lane to be used for other lanes. This clocking mode is used when several lanes are part of the same protocol using the same clock.

  • Page 57: Figure 31 Non-Deterministic Interface With Fwf

    Functional Description In the transmit direction, data from the fabric or PCS is passed through the FWF with a clock from the FWF ensuring synchronous clock and data relationships passing to the PMA interface. The FWF is optionally selected in the Libero Transceiver Configurator by choosing the correct global or regional interface clock option, see Table 32, page 94.

  • Page 58: Deterministic Interface

    Functional Description 3.4.2 Deterministic Interface Low-latency regional clocks with a specific mode of the FWF are used when a zero-cycle path is required; for example, by protocols such as CPRI and JESD204B that require both receive and transmit paths have a fixed deterministic latency as expressed in number of clock cycles. In this case, data is interfaced directly to capture registers while the clock is routed on regional clock resources.

  • Page 59: Transceiver Clock Regions

    Functional Description Figure 36 • Deterministic Transceiver Receive Timing Waveform RX_CLK RX_CLK (at fabric FF) RXDATA Valid Note: RXCLK_FABRIC at PCS I/F after Regional clock route 3.4.3 Transceiver Clock Regions Two regional clock buffers per transceiver lane (eight per transceiver quad) come from the transceiver. These interconnections are the basis for specific regions that the particular Quads can drive.

  • Page 60: Transceiver Data Path Latency

    Functional Description Users need to understand the regional clock implications when targeting designs that may migrate to different device sizes. The user should also use this in pin planning of boards when desiring to drive I/O from the transceiver clocks. Table 14 •...

  • Page 61: Transceiver Clocking Use Cases

    Functional Description 3.4.5 Transceiver Clocking Use Cases Each transceiver quad can source a global clock directly. Transceiver designs should use regional clocks for the interface logic when possible. This reduces over use of global clocks. In many cases, transceiver designs can share global clocks when multiple interfaces are used, depending on protocol requirements. Only one global clock is supported per transceiver quad.

  • Page 62: Transceiver Clocking

    Functional Description Typically, these interfaces are implemented uni-directional. For full duplex, the RX interface and TX interface clock can not be global or global (Shared) at the same time as only one global clock is supported per transceiver quad. If using the RX and TX both as global is required by design, the design must use two separate XCVR configurations (instances), one in RX half duplex mode and other in TX half duplex mode.

  • Page 63: Table 17 Transmit Pll

    Functional Description Q#_TXPLL_SSC: This PLL operates in the 1.6 GHz – 6.4 GHz frequency range and can provide a transmit bit clock to a transceiver quad. The TxPLL_SSC supports jitter attenuation for loop-time applications. Unique to this PLL is the spread-spectrum clocking (SSC) generation support, which can generate a saw-tooth clock with various options.

  • Page 64: Spread Spectrum Clocking

    Functional Description 3.5.2 Spread Spectrum Clocking TxPLL produces spread spectrum clock generation (SSCG). SSCG uses a modulated output clock signal to reduce peak EMI. The lowering of peak EMI enables significant reduction in expensive shielding cost or reduce interference with other sensitive circuits. By modulating the PLL, the resulting spectrum at each clock harmonic is made broad-band or flattened, and reduced in amplitude from 10 db to 20 dB, depending on frequency and modulation amplitude.

  • Page 65: Transmit Lane Alignment

    Functional Description 3.5.3 Transmit Lane Alignment Applications like Serial RapidIO, XAUI, DisplayPort, Interlaken, and JESD204B need transmit alignment across multiple lanes. Transmit lane alignment depends on the number of lanes, total skew, fabric clock frequency relative to the line rate, and number of TX PLLs. The method of alignment involves launching a reset from the shared PLL to each TX lane after the PLLs are locked.

  • Page 66: Figure 41 Using Txplls For Upto Four Lanes

    Functional Description Figure 41 • Using TXPLLs For Upto Four Lanes TX_Bit_CLK TXPLL1 TX_CLK_RESET QUAD TX_Bit_CLK TX Lane TX_CLK_RESET TX_Bit_CLK TX_Bit_CLK TX Lane TX_CLK_RESET TXPLL_SSC TX_Bit_CLK TX_CLK_RESET TX Lane TX_CLK_RESET TX_Bit_CLK TX Lane TX_CLK_RESET TX_Bit_CLK TXPLL0 TX_CLK_RESET QUAD TX_Bit_CLK TX Lane TX_CLK_RESET TX_Bit_CLK TX_Bit_CLK...

  • Page 67: Figure 42 Fpga Logic For Tx Alignment (5 To 8 Lanes)

    Functional Description In these scenarios, the transceiver uses two PLLs with the same reference clock and a separate fabric logic for reset of the TX lanes as shown in Figure 42, page 60. Figure 42 • FPGA Logic For TX Alignment (5 to 8 Lanes) PF_XCVR Any low skew clock not from Tx or Rx SerDes lane clocks that is at the same rate or slower...

  • Page 68: Transceiver Clocks

    Functional Description 3.5.4 Transceiver Clocks The transceiver transmitters have high-performance bit clocks running at half the line rate of the fastest transmit lane driven by the clock. The transmit PLLs generate these clocks based on a transmit reference clock, with the configuration set in the Libero design software. Within each lane, the transmit bit-rate clock (Figure 6, page 14) is divided by 1 (full rate), 2, 4, 8, or 11 to...

  • Page 69: Figure 43 Reference Clock (Refclk) Interface To Transmit Pll

    Functional Description Figure 43 • Reference Clock (REFCLK) Interface to Transmit PLL Cascade from Upper REFCLK To Local Quad CDRs TXPLL PLL_LOCK REFCLK0 REF_CLK LOCK CLKS_TO_XCVR[BIF] REFCLK1 BIT_CLK REF_CLK_TO_LANE TXPLL= TXPLL_SSC or REFCLK TXPLL0 or TXPLL1 Interface Cascade to Lower The following table lists the transmit PLL pins.

  • Page 70: Figure 44 Typical Jitter Attenuator Application Scheme

    Functional Description 3.5.4.2 Jitter Attenuator All transmit PLLs support a jitter-attenuator option. The jitter attenuator is used to track the data rate of any noisy reference clock with a clean input reference clock to provide a 0 ppm offset from the noisy reference clock while providing a jitter-cleaned output.

  • Page 71: Figure 45 Jitter Attenuation Txpll

    Functional Description Select Jitter Cleaning Mode under the Clock Options and choose the targeted protocol templates from the drop-down as shown in the following figure. Figure 45 • Jitter Attenuation TXPLL Jitter attenuation PLL presets can be selected with TX PLL configurator (and the enable JA_CLK port in XCVR configurator).

  • Page 72: Figure 46 Japll Custom Protocol Setting

    Functional Description 3.5.4.2.1 Custom Protocol Settings Full duplex jitter attenuation solution is available for custom protocols in Libero SoC v12.3 or later. This support is for one refclk and one data rate allowing user the flexibility to create designs requiring customized settings not already supported by the presets.

  • Page 73: Figure 49 Dedicated Transceiver Reference Clock Inputs

    Functional Description 3.5.4.3 Dedicated Reference Clock Input Pins For every transmit PLL within the transceiver PMA, there is a reference input pin pair for an external input of reference clocks to the device, as shown in the following figure. The reference clock inputs provide flexibility to interface with both single-ended and differential clocks and can drive up to two independent clocks per transceiver quad.

  • Page 74: Table 20 Xcvr Refclk Defaults

    Functional Description 3.5.4.3.2 Reference Voltage Input In this mode, the input interface supports two single-ended modes: • Local reference input: a reference voltage is connected to the XCVR_REFCLK_N input, which is used for the clock connected to the XCVR_REFCLK_P input. The resulting reference clock is available on the REFCLK0 output (REFCLK1 output is unavailable with local reference input mode).

  • Page 75: Table 21 Reference Clock Input Buffer Standards

    Functional Description Reference clock input buffer Standards Table 21 • Reference voltage (Not supported Single ended Differential for ES/XT devices). LVCMOS18 (VDDI = 2.5) HCSL25 HSUL18I (VDDI = 2.5) LVCMOS25 (VDDI = 2.5) LVDS25 HSUL18II (VDDI = 2.5) LVCMOS33 (VDDI = 3.3) LVPECL33 (VDDI = 3.3) SSTL18I (VDDI = 2.5) LVTTL (VDDI = 3.3)

  • Page 76: Figure 50 Refclk Input Pin Diagram

    Functional Description Figure 50 • REFCLK Input Pin Diagram XCVR_#A_REFCLK Reference To Local Quad Clock Interface XCVR_#B_REFCLK TXPLLs and CDRs Block XCVR_#C_REFCLK XCVR_#A_REFCLK Reference To Local Quad Clock Interface XCVR_#B_REFCLK TXPLLs and CDRs Block XCVR_#C_REFCLK To Cascade Clock Note: The XCVR_#[ABC]_REFCLK pins are available per quad. The REFCLK input to the reference clock interface (see Figure 43, page 62) connects the REFCLK source to the associated TxPLL.

  • Page 77: Figure 51 Mpf100 Transceiver And Transmit Pll Layout

    Functional Description MPF200-FCG484 and FCVG484 packages only support up to eight XCVR lanes and six TXPLLs. Figure 51, page 70, Figure 52, page 71, and Figure 53, page 72 shows the arrangement of the transceiver quads, the connectivity of lanes, transmit PLLs, and embedded PCIe blocks for the MPF100, MPF200, MPF300, and MPF500 device.

  • Page 78: Figure 52 Mpf200 And Mpf300 Transceiver And Transmit Pll Layout

    Functional Description Figure 52 • MPF200 and MPF300 Transceiver and Transmit PLL Layout Q2_TXPLL0 Q2_LANE3 Q2_LANE2 Q2_TXPLL_SSC Q2_LANE1 Q2_LANE0 Q2_TXPLL1 PCIE1 Q0_TXPLL1 Q0_LANE3 Q0_LANE2 Q0_TXPLL_SSC Q0_LANE1 Q0_LANE0 Q0_TXPLL0 PCIE0 Q1_TXPLL1 Q1_LANE3 Q1_LANE2 Q1_TXPLL_SSC Q1_LANE1 Q1_LANE0 Q1_TXPLL0 Q3_LANE3 Q3_LANE2 Q3_TXPLL_SSC Q3_LANE1 Q3_LANE0 Q3_TXPLL Note: MPF200 –...

  • Page 79: Figure 53 Mpf500 Transceiver And Transmit Pll Layout

    Functional Description Figure 53 • MPF500 Transceiver and Transmit PLL Layout Q4_LANE3 Q4_LANE2 Q4_TXPLL Q4_LANE1 Q4_LANE0 Q4_TXPLL_SSC Q2_TXPLL0 Q2_LANE3 Q2_LANE2 Q2_TXPLL_SSC Q2_LANE1 Q2_LANE0 Q2_TXPLL1 PCIE1 Q0_TXPLL1 Q0_LANE3 Q0_LANE2 Q0_TXPLL_SSC Q0_LANE1 Q0_LANE0 Q0_TXPLL0 PCIE0 Q1_TXPLL0 Q1_LANE3 Q1_LANE2 Q1_TXPLL_SSC Q1_LANE1 Q1_LANE0 Q1_TXPLL1 Q3_LANE3 Q3_LANE2 Q3_TXPLL_SSC...

  • Page 80: Pma And Pcs Resets

    Functional Description PMA and PCS Resets The PolarFire transceiver uses partitioned resets, one single wire for PMA_ARST_N and one for PCS_ARST_N to the PF_XCVR. Specifically, these two inputs can come from the FPGA fabric to reset the PMA and PCS portions of the transceiver. Both inputs assert the reset asynchronously and de- assertion is internally synchronized.
  • Page 81 Functional Description The functionality of the resets are register configured by the Libero software. See the PolarFire Device Register Map for information about register maps. After Libero programming, these register controlled bits are written at power up prior to releasing the Tx PLL from reset. By doing this configuration during reset guarantees that the PCS Tx is reset without manual intervention.

  • Page 82: Pcs Rate Switch Between 8B10B And 64B66B Mode For Cpri

    Functional Description PCS Rate Switch Between 8b10b and 64b66b Mode for CPRI All CPRI protocol data rates are statically supported with the Libero Transceiver Configurator using either 8b10b or 64b66b modes. 8b10b supports CPRI rates 2, 3, 4, 5, 6, and 7 while 64b66b mode supports rates 7a, 8, and 9.
  • Page 83 Functional Description Port Crossover between the 8b10b and 64b66b Modes Table 23 • DIRECTION 8B10B MODE 64B6xB MODE Input TX_DISPFNC[0] RESERVED_IN[13] Input TX_K[7:6] RESERVED_IN[15:14] Input TX_K[5] RESERVED_IN[16] Input TX_K[4] TX_SOS Input TX_K[3:0] TX_HDR[3:0] Input TX_DATA[63:33] TX_DATA[63:33] Input TX_DATA[32:19] TX_DATA[32:19] Input TX_DATA[18:17] TX_DATA[18:17] Input...
  • Page 84 Functional Description Port Crossover between the 8b10b and 64b66b Modes Table 23 • DIRECTION 8B10B MODE 64B6xB MODE Output RX_DATA[63:51] RX_DATA[63:51] Output RX_DATA[50:49] RX_DATA[50:49] Output RX_DATA[48:9] RX_DATA[48:9] Output RX_DATA[8:5] RX_DATA[8:5] Output RX_DATA[4] RX_DATA[4] Output RX_DATA[3:1] RX_DATA[3:1] Output RX_DATA[0] RX_DATA[0] Input TX_BIT_CLK* Input TX_PLL_LOCK*...

  • Page 85: Table 24 System Registers Affecting 8B10B And 64B6Xb Data Paths

    Functional Description The following table outlines the affected registers that must be modified during rate switching. System Registers Affecting 8B10B and 64B6xB Data Paths Table 24 • Register Required Value for Required Value for Page xls Register Name Field Name Description 8B10B 64B6xB...
  • Page 86 Functional Description System Registers Affecting 8B10B and 64B6xB Data Paths (continued) Table 24 • Register Required Value for Required Value for Page xls Register Name Field Name Description 8B10B 64B6xB pcslane LCLK_R0 LCLK_PCS_RX Defines clock Must be set to 2’d3 for 2’d3 _CLK_SEL [1:0] module’s source for...
  • Page 87 Functional Description System Registers Affecting 8B10B and 64B6xB Data Paths (continued) Table 24 • Register Required Value for Required Value for Page xls Register Name Field Name Description 8B10B 64B6xB pma_lane DES_CLK_CTRL DESMODE[2:0] Selects parallel bus Must select the 40-bit Must select the 32- width of deserializer wide bus mode for...

  • Page 88: Implementation

    Implementation Implementation PolarFire transceiver blocks support many high-speed serial protocols. These protocols are supported using multiple transceiver building blocks that the user constructs using the transceiver configurators in the Libero design software. The Libero configurator allows the user to set the reference clock and data rates for particular protocols.

  • Page 89: Transceiver Reference Clock Configurator

    Implementation 4.1.1 Transceiver Reference Clock Configurator The Transceiver Reference Clock Configurator is used to build the correct reference clock input to the transceiver and to the Tx PLL. The user can pick the input type and various input options. To initiate the Reference Clock Configurator, perform the following steps: Access the Transceiver Reference Clock cores under PolarFire Features from the Catalog window, as shown in the following figure.

  • Page 90: Figure 57 Transceiver Reference Clock Configurator Gui

    Implementation Figure 57 • Transceiver Reference Clock Configurator GUI The following tables lists transceiver reference clock configurator GUI options. Transceiver Reference Clock Configurator GUI Options Table 26 • Options Default Details Reference Clock 0 configuration Enable reference clock 0 Enable and disable Enabled Checked = enabled Reference Clock 0 Mode...

  • Page 91: Figure 58 Transceiver Reference Clock Mode Type

    Implementation Select the reference clock mode type based on the input buffer type in the application. Single-ended Differential is the default mode. Figure 58 • Transceiver Reference Clock Mode Type In the case of LVCMOS or Voltage Reference inputs, the design can have up to two individual reference clock inputs in one instance of the PF_XCVR_REF_CLK.

  • Page 92: Figure 61 Pf_Xcvr_Ref_Clk With Differential Input And Single Output Clock

    Implementation Figure 61 • PF_XCVR_REF_CLK With Differential Input and Single Output Clock Optionally enable a connection to the FPGA fabric for either/both reference clock 0 or reference clock 1. When enabled, a related port of the associated reference clock is exposed for fabric routing. Figure 62 •...

  • Page 93: Transmit Pll Configurator

    Implementation 4.1.2 Transmit PLL Configurator The Transceiver Transmit PLL Configurator is used to build the correct transmit PLL to the transceiver. The user can pick from many of the PLL options used for the transceiver based on the application. To initiate the Transceiver Transmit PLL Configurator, perform the following steps: Access the Transmit PLL module under PolarFire Features from the Catalog window, as shown in the following figure.

  • Page 94: Figure 64 Transmit Pll Configurator Gui

    Implementation Double-click each PF_TX_PLL block from the catalog to launch the configurator. A GUI allows the option of selecting the related transmit PLL properties. Figure 64 • Transmit PLL Configurator GUI The following table lists the transmit PLL configurator GUI options. Transmit PLL Configurator GUI Options Table 27 •...

  • Page 95: Figure 65 Clock Inputs

    Implementation Transmit PLL Configurator GUI Options Table 27 • Clock Inputs Options Default Details Jitter Cleaning Mode Enable and disable Disabled Radio-button on = disabled The following options are available when enabled: 10G SyncE 32Bit 10G SyncE 64Bit 1G SyncE 10Bit CPRI Rate 1 CPRI Rate 2 CPRI Rate 3...

  • Page 96: Figure 67 Clock Options

    Implementation Normal Mode configures the TX PLL to default operation based on the clock Inputs/Outputs setting. Whereas, Jitter Cleaning mode customizes the attenuation coefficients for the pre-defined standards to be used where the recovered clock can be used as a TX reference clock to meet protocol jitter specifications.

  • Page 97: Figure 70 Enable Dynamic Reconfiguration Interface

    Implementation Spread Spectrum Table 28 • Options Default Details Modulation Frequency Target User entry 64 KHz Target Spread Spectrum modulation. Calculated 60.0962 KHz Calculation is based on TXPLL reference clock settings. Spread Mode Down spread/Center Down Configures the modulation style Spread Spread/Divval Spread...

  • Page 98: Transceiver Interface Configurator

    Implementation The TxPLL supports an additional clock output. This CLK_125 output port is automatically exposed when TxPLL BIT_CLK is 5 Gbps. This clock is used with the PCIE macro as input to the transaction layer or AXI clock. For more information about CLK_125, see UG0685: PolarFire FPGA PCI Express User Guide.

  • Page 99: Figure 73 Transceiver Interface Configuration Gui

    Implementation Double-click each PF_XCVR block in the catalog to launch the configurator. A GUI allows the option to select the related XCVR properties. Figure 73 • Transceiver Interface Configuration GUI The following tables list Transceiver Interface options. Transceiver Interface General Settings Table 29 •...

  • Page 100: Table 31 Transceiver Interface Pcs Settings

    Implementation Transceiver Interface PMA Settings Table 30 • PMA Settings Options Default Details RX Data rate 250 Mbps – 12700 Mbps 5000 Mbps 10312.5 Mbps (STD maximum) RX CDR lock mode Lock to reference, Lock to data, Lock to data Burst Mode Receiver , lock to data with 2x gain...

  • Page 101: Table 32 Clocks And Resets

    Implementation TX_CLK_G/R frequency = RX_CLK_G/R frequency = FPGA Interface frequency = data rate/(PMA-PCS width × PCS Gearing). Clocks and Resets Table 32 • Interface Options Options Default Details When Use as PLL reference clock is selected, Interface clock Use as PLL reference clock Disabled this exposes additional ports that permit connection to the PLL REFCLKs.

  • Page 102: Figure 74 Pma Mode-Enable Cdr Bit-Slip Port

    Implementation connected to the fabric resources. The dedicated CDR_REF_CLK_0/1 port must be connected to the REF_CLK or REF_CLK_0/1 output of the PF_XCVR_REF_CLK block. Select PCS-Fabric interface width from the GUI. This selection computes the FPGA interface frequency. The FPGA interface frequency is calculated based on the transceiver data rate, PCS-Fabric width, and the PCS settings/mode.

  • Page 103: Figure 77 Xcvr Component With Dri Port Enabled

    Implementation Figure 77 • XCVR Component With DRI Port Enabled 12. After making all of the selections in the Transceiver Interface Configurator, click OK. When the transceiver interface configuration is complete, a PF_XCVR macro is generated by the Libero Software. The macro includes the ports based on the configuration. Figure 79, page 97 to Figure 82,...

  • Page 104: Figure 79 Pma Only Pcs Example Smartdesign Component

    Implementation Figure 79 • PMA Only PCS Example SmartDesign Component Figure 80 • 8b10b PCS Example SmartDesign Component Figure 81 • 64b66b PCS Example SmartDesign Component Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0...

  • Page 105: Figure 82 Soft Pipe Pcs Example Smartdesign Component

    Implementation Figure 82 • Soft PIPE PCS Example SmartDesign Component After building the PF_XCVR, PF_TX_PLL and PF_XCVR_REF_CLK cores, the transceiver subsystem must be connected together in the SmartDesign canvas. Typically, the REF_CLK and/or FAB_REF_CLK outputs of the PF_XCVR_REF_CLK are connected to the respective inputs of the PF_XCVR and the input REF_CLK of the PF_TX_PLL.

  • Page 106: Transceiver Modes

    Implementation Figure 84 • Completed Transceiver Subsystem with ERM See the port list tables in Transceiver PCS Interface Modes, page 23 for complete pin descriptions generated with the Transceiver Configurator. Transceiver Modes The transceiver architecture permits several ways to use the transmit and receive portions of the PMA and PCS.

  • Page 107: Half-Duplex Mode

    Implementation Full-duplex configures the XCVR with common Tx and Rx data rates. Although, users can see independent control for data rate and PCS-Fabric widths, a Libero SoC DRC prevent users from selecting different rates/widths when TX and RX is in full-duplex mode. In full-duplex mode, the user must match the Rx and Tx requirements.

  • Page 108: Libero Generated Files

    Implementation Libero Generated Files Libero SoC software automatically generates the required files after stepping through the design entry steps of the transceiver. The following files are created: • Netlist file—the RTL netlist instantiates the transceiver macros and related RTL wrappers based on protocol specific functions.

  • Page 109: Figure 86 Derive Constraints Using Constraints Editor

    Implementation create_clock -period <T> [get_pins {LANE<n>/RX_CLK_R}] Users need to use the Derived SDC file generated by clicking the Derive Constraints in the Timing tab of the Constraint Manager window of Libero SoC software. The following example shows a Libero project with transceiver. create_clock -name {REF_CLK_PAD_P} -period 6.4 [ get_ports { REF_CLK_PAD_P } create_clock -name {My_Project_0/my_xcvr_0/PF_XCVR_0/LANE0/TX_CLK_R} -period 16 [ get_pins { My_Project_0/my_xcvr_0/PF_XCVR_0/LANE0/TX_CLK_R } ]...

  • Page 110: Physical Constraints

    Implementation 4.4.2 Physical Constraints Transceiver designs require physical constraints. These constraints provide placement guidance for the embedded transceiver blocks such as XCVR_REF_CLK, XCVR_TXPLL, and XCVR. Select the placement of the RXD and TXD transceiver pins and reference clock input pins by adding location constraints to the design PDC file.

  • Page 111: Adding Physical Constraints Using Libero

    Implementation 4.4.2.1 DFE Coefficients DFE Calibration of the DFE Coefficients is not be performed in Static DFE. See DFE Calibration, page 12. To set the required registers with static values, users must enhance the “set_io” PDC command to add new attributes. The new attributes that need to be added are highlighted in the below PDC command. PDC command example: set_io -port_name LANE0_RXD_N -RX_DFE_COEFFICIENT_H1...

  • Page 112: Invoking The Pin Planner

    Implementation 4.5.1 Invoking the Pin Planner To invoke the Pin Planner, the design must be in the post-synthesis state. Invoke the Constraint Manager from the Design Flow window (Design Flow > Manage Constraints > Open Manage Constraints View). In the Constraints Manager, select the I/O Attributes tab and then select Edit > Edit with I/O Editor (I/O Attributes >...

  • Page 113: Figure 88 Xcvr Placement Tab

    Implementation Figure 88 • XCVR Placement Tab The following figure shows the XCVR Signal Integrity View tab. When user selects lane in Left Panel, the user can view and change the signal integrity parameters for the Rx and Tx transceiver ports. Figure 89 •...

  • Page 114: Transceiver Initialization

    Implementation Transceiver Initialization The transceiver is initialized after the user customizes the transceiver or PCIe features with the associated configurators. The transceiver initialization data refers to the memory files and the initialization clients required for the three stages of initialization that is executed by the device at start-up. For proper functioning, the user design must generate initialization data before programming (running Generate Bitstream or the Export Programming File, Export Programming Job, Export Programming Job Data, Export SmartDebug Job Data, Generate SPI Flash Image, Generate SPI Flash Image, and Export...

  • Page 115: Signal Integrity Conditioning

    Signal Integrity Conditioning Signal Integrity Conditioning The PolarFire transceivers have many tuning adjustments for the analog portions of the PMA allowing for signal integrity optimizations to the system. These features include Rx Continuous Time Line Equalization (CTLE), Rx termination, polarity inversion, Pre- and Post-cursor output emphasis, output impedance settings, and Tx amplitude adjustment.

  • Page 116: Transmitter

    Signal Integrity Conditioning Building a transceiver based design using Libero SoC software flow allows flexibility to improve the PolarFire transceiver performance within the system. The PolarFire software sets initial good defaults for the user's custom design based on input information to the transceiver configurators. The user can change the associated transceiver input and output settings using the IO Editor after initial design generation.

  • Page 117: Receiver

    Signal Integrity Conditioning Receiver The receiver deserializes high-speed serial data received through the input buffer by creating a parallel data stream for the FPGA fabric and recovering the clock information from the received data. For more information about receiver, see Receiver, page 7.

  • Page 118: Loss-Of-Signal Detector

    Signal Integrity Conditioning 5.2.5 Loss-of-Signal Detector Loss-of-signal (LOS) detector (low and high value) sets the requirement of the voltage detector. The following table lists the upper and lower set points for a LOS to ensure that a good signal is applied into the receiver.

  • Page 119: Io Editor-Signal Integrity

    Signal Integrity Conditioning 5.3.1 IO Editor—Signal Integrity To access the Signal Integrity tab from IO Editor: Open Constraint Manager > Edit > Edit with I/O Editor. Figure 91 • IO Editor—XCVR View In the XCVR View [active] tab, select Signal Integrity View tab and the XCVR lane to edit signal integrity settings as shown in the following figure.

  • Page 120: Table 37 Tx Attributes And Values

    Signal Integrity Conditioning 5.3.2.1 PDC Supported Attributes and Values The following table list the PDC supported attributes and values. For more information about he description of the attributes, see Transmitter, page 109. Table 37 • TX Attributes and Values Name Direction Values Default...

  • Page 121: Table 38 Rx Attributes And Values

    Signal Integrity Conditioning TX Attributes and Values Table 37 • Name Direction Values Default TX_TRANSMIT_COMMON_MODE_ Output ADJUSTMENT The following table list the PDC supported attributes and values. For more information about he description of the attributes, see Receiver, page 110. Table 38 •...
  • Page 122 Signal Integrity Conditioning RX Attributes and Values (continued) Table 38 • Name Direction Values Default RX_LOSS_OF_SIGNAL_ Input DETECTOR_HIGH PCIE SATA POLARITY Input Normal Normal Inverted Microsemi Proprietary and Confidential UG0677 User Guide Revision 9.0...

  • Page 123: Smartdebug Signal Integrity

    Signal Integrity Conditioning SmartDebug Signal Integrity SmartDebug signal integrity is invoked from debug transceiver. SmartDebug Signal Integrity helps to evaluate the reliability of a high-speed serial link using PolarFire transceivers. The signal integrity GUI follows the same format as the IO Editor. For more information about software operation, Guide.

  • Page 124: Loopback Modes

    Signal Integrity Conditioning 5.4.1 Loopback Modes Loopback operations are embedded within the PolarFire XCVR and are commonly used in debug practice. These loop backs can be tested solely within the device by sending and receiving on-chip or can test real-data to and from the system side. For information, see Loopback, page 122.

  • Page 125: Eye Monitoring

    Signal Integrity Conditioning Monitor the Lock indicators and error counters to check the quality of the link. This test ensures proper power supplies, clocks and resets to the XCVR and traffic is not going off-chip to the system. The following figures show the Smart BERT options of the debug transceiver. Figure 95 •...

  • Page 126: Figure 97 Eye Monitor Plot

    Signal Integrity Conditioning The plot produces an eye diagram by overlaying many bits whereas a color gradient shows the density hits of the signal. Thus, the opening is represented as the area with least hits. Click the Eye Monitor tab in the Debug TRANSCEIVER window to see the eye monitor representation within the receiver.

  • Page 127: Figure 98 Example Of Optimize Dfe

    Signal Integrity Conditioning 5.4.3.2 SmartDebug Decision Feedback Equalization Support SmartDebug is used to adapt the DFE coefficients to optimize the settings for the overall signal integrity at the receiver for the system under test environment. On-demand, the SmartDebug utility runs the adaptive algorithm to of the DFE filter to resolve the TAP values of the DFE coefficients.

  • Page 128: Simulation

    Simulation Simulation RTL simulation mode is available for all of the transceiver modes. This simulation mode enables the simulation of all the protocol communication layers (including the PMA, PCS, and fabric interfaces) and provides accurate cycle simulation for the design. However, using RTL simulation incurs some run-time penalties.

  • Page 129: Debug And Testing

    Debug and Testing Debug and Testing PolarFire FPGA include debug and testing features for multi-gigabit transceivers. It provides capabilities for diagnostic test setups and inserting test patterns during FPGA testing and debugging. This chapter describes the embedded transceiver capabilities that allow high-speed link diagnostics. PRBS Generator/Checker Each PolarFire FPGA transceiver has embedded blocks with a built-in PRBS generator and checker that can be used to perform link testing and diagnostics.

  • Page 130: Figure 100 Transceiver Loopbacks

    Debug and Testing This loopback is after the CDR which requires the receive and transmit paths to have exactly matched clock rates or 0 ppm differences. In the Far-end loopback case, the LANE#_RX_READY must be used instead of LANE#_RX_VAL to indicate valid data path. Figure 100 •...

  • Page 131: Dynamic Reconfiguration Interface

    Debug and Testing Dynamic Reconfiguration Interface The dynamic reconfiguration interface (DRI) is used with PolarFire transceiver to access the memory map of the transceiver blocks. DRI is an APB slave that allows global access to all transceiver lanes, PCIe blocks, transmit PLLs, and FPGA PLLs. The DRI allows changing key features of the transceiver before and during operation.

  • Page 132: Board Design Recommendations

    Board Design Recommendations Board Design Recommendations User must have knowledge of the following PCB design topics before designing a PCB that uses PolarFire transceivers. • Device interfacing • Transmission line impedance and routing • Power supply design filtering and distribution •...
  • Page 133 Board Design Recommendations Transceiver Device Level Pin List (continued) Table 39 • Pin Name Direction Description XCVR_#_RX2_N Input Receive data. Transceiver differential negative input. Each transceiver quad consists of four receive– signals. XCVR_#_RX1_N Input Receive data. Transceiver differential negative input. Each transceiver quad consists of four receive–...

  • Page 134: Design For Protocols

    Board Design Recommendations Design for Protocols Transceiver designs are used in many high-speed protocols. Each protocol specifies the system requirements to meet the specific standards of the protocol. The electrical performance requirements for these protocols must be addressed by proper design of the PCB. The following sections describes the PCB requirements of PolarFire transceivers for specific protocols.

  • Page 135: Jesd204B

    Board Design Recommendations Note: The ceramic 0201 and 0402 AC coupled capacitors are preferred for PolarFire FPGA transceivers. The transmitter must have AC coupling capacitors. 8.2.2 JESD204B JESD204B version increases the supported lane data rates to 12.5 Gbps and divides devices into three different speed grades.

  • Page 136: Unused Transceiver Pins

    Board Design Recommendations 8.3.1 Unused Transceiver Pins If the transceiver interface is not used in the design, the transceiver pins must be connected as defined in the related PolarFire Package Pin Assignment Table (PPAT). Transceivers Insertion Loss The following table lists the type of insertion loss. Table 40 •...

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