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Microchip Technology Microsemi UG0677 Manuals
Manuals and User Guides for Microchip Technology Microsemi UG0677. We have
1
Microchip Technology Microsemi UG0677 manual available for free PDF download: User Manual
Microchip Technology Microsemi UG0677 User Manual (136 pages)
PolarFire FPGA Transceiver
Brand:
Microchip Technology
| Category:
Transceiver
| Size: 4 MB
Table of Contents
Table of Contents
3
1 Revision History
8
Revision 9.0
8
Revision 8.0
8
Revision 7.0
8
Revision 6.0
8
Revision 5.0
9
Revision 4.0
9
Revision 3.0
9
Revision 2.0
9
Revision 1.0
10
2 Overview
11
Table 1 Supported Serial Protocols
11
Figure 1 Transceiver Lane Overview
12
Features
13
3 Functional Description
14
Pma
14
Receiver
14
Figure 2 Transceiver Receiver
15
Figure 3 Receiver Input Buffer
15
Figure 4 Input Signal Path
16
Figure 5 CDR Lock Mode Options
18
Table 2 CDR Lock Mode Values
18
Table 3 Mode of Operations
20
Transmitter
21
Figure 6 Transceiver Transmitter
21
Figure 7 Transmit Output Driver
22
Enhanced Receiver Management
23
Table 4 ERM Ports
23
Figure 8 Enhanced Receiver Management in XCVR Configurator
24
Figure 9 Calibration Options for Enhanced Receiver Management Operations
25
Figure 10 Exposing RX_READY_CDR and RX_VAL_CDR Pins
25
Figure 11 DFE Options
26
Table 5 DFE Options
26
Figure 12 First Lock Calibration Waveform
27
Figure 13 Disruption of Serial Rx Data Stream
27
Figure 14 Restart after Initialization
28
Figure 15 On-Demand Calibration Waveform
29
Transceiver PCS Interface Modes
30
8B10B
30
Figure 16 8B10B Data Path
32
Table 6 System Registers Affecting 8B10B Data Path
33
Table 7 8B10B Port List
34
64B66B/64B67B
37
Table 8 64B6Xb Transmit Data Path Blocks, Fabric to PMA Order
37
Figure 17 64B6Xb Data Path
38
Table 9 64B6Xb Receive Data Path Blocks, PMA to Fabric Order
38
Table 10 System Registers Affecting 64B6Xb Data Path
39
Figure 18 64B66B Receive Sequence for 32-Bit Interface
40
Figure 19 64B66B Receive Sequence for 64-Bit Interface
40
Figure 20 64B66B Transmit Sequence for 64-Bit Interface
41
Figure 21 64B66B Transmit Sequence for 32-Bit Interface
41
Figure 22 64B67B Transmit Sequence for 32-Bit Interface
42
Figure 23 64B67B Receive Sequence for 32-Bit Interface
43
Table 11 64B66B/64B67B Port List
43
Pipe
45
Table 12 PIPE Port List
46
PIPE Interface Compliance Exceptions
50
Figure 24 Initial Receiver Detection Response for Receiver-Not-Present
50
PMA Only
51
Figure 25 Initial Receiver Detection for Receiver-Present
51
Figure 26 Subsequent Receiver Detection Where Prior Status was Receiver-Not-Present
51
Figure 27 PMA-Bus Waveform
52
Figure 28 PMA Only Data Path - 80-Bits
52
Figure 29 PMA Only Data Path - Less than or Equal to 40-Bits
53
Table 13 PMA Port List
53
PCS/FPGA Fabric Interface
55
Non-Deterministic Interface
56
Figure 30 Global-Shared Clocking Example
56
Figure 31 Non-Deterministic Interface with FWF
57
Figure 32 Non-Deterministic Interface Transmit Timing Waveform
57
Figure 33 Non-Deterministic Transceiver Receive Timing Waveform
57
Deterministic Interface
58
Figure 34 Deterministic Timing Interface
58
Figure 35 Deterministic Transceiver Transmit Timing Waveform
58
Transceiver Clock Regions
59
Figure 36 Deterministic Transceiver Receive Timing Waveform
59
Figure 37 Transceiver Clock Regions
59
Transceiver Data Path Latency
60
Table 14 Clock Region Connectivity
60
Table 15 Transceiver Data Path Latency
60
Transceiver Clocking Use Cases
61
Table 16 Transceiver Interface Clocking Use Cases
61
Transceiver Clocking
62
Transmit PLL
62
Figure 38 Transmit PLL
62
Table 17 Transmit PLL
63
Spread Spectrum Clocking
64
Figure 39 Spread Spectrum Clocking Modulation Mode
64
Transmit Lane Alignment
65
Figure 40 Using TXPLL_SSC for Upto Four Lanes
65
Figure 41 Using Txplls for Upto Four Lanes
66
Figure 42 FPGA Logic for TX Alignment (5 to 8 Lanes)
67
Transceiver Clocks
68
Figure 43 Reference Clock (REFCLK) Interface to Transmit PLL
69
Table 18 Transmit PLL Pin List
69
Figure 44 Typical Jitter Attenuator Application Scheme
70
Figure 45 Jitter Attenuation TXPLL
71
Table 19 Jitter Attenuation PLL Presets
71
Figure 46 JAPLL Custom Protocol Setting
72
Figure 47 Reference Clock Source Options
72
Figure 48 Rx JA Clock Frequency (XCVR Configurator)
72
Figure 49 Dedicated Transceiver Reference Clock Inputs
73
Table 20 XCVR REFCLK Defaults
74
Table 21 Reference Clock Input Buffer Standards
75
Figure 50 REFCLK Input Pin Diagram
76
Table 22 Polarfire Transceiver Resources
76
Figure 51 MPF100 Transceiver and Transmit PLL Layout
77
Figure 52 MPF200 and MPF300 Transceiver and Transmit PLL Layout
78
Figure 53 MPF500 Transceiver and Transmit PLL Layout
79
PMA and PCS Resets
80
Figure 54 PMA_ARST_N Block Diagram
80
PCS Rate Switch between 8B10B and 64B66B Mode for CPRI
82
Figure 55 PCS Rate Switch between 8B10B and 64B66B Mode
82
Table 23 Port Crossover between the 8B10B and 64B66B Modes
82
Table 24 System Registers Affecting 8B10B and 64B6Xb Data Paths
85
4 Implementation
88
Libero Configurators
88
Table 25 Transceiver Configurator Component List
88
Figure 56 Transceiver Reference Clock Selection from Catalog
89
Transceiver Reference Clock Configurator
89
Figure 57 Transceiver Reference Clock Configurator GUI
90
Table 26 Transceiver Reference Clock Configurator GUI Options
90
Figure 58 Transceiver Reference Clock Mode Type
91
Figure 59 PF_XCVR_REF_CLK with One Single-Ended Input and Single Output Clock
91
Figure 60 PF_XCVR_REF_CLK with Two Single-Ended Input and Two Output Clock
91
Figure 61 PF_XCVR_REF_CLK with Differential Input and Single Output Clock
92
Figure 62 PF_XCVR_REF_CLK with Fabric Output Clock
92
Figure 63 Transceiver Transmit PLL Selection from Catalog
93
Transmit PLL Configurator
93
Figure 64 Transmit PLL Configurator GUI
94
Table 27 Transmit PLL Configurator GUI Options
94
Figure 65 Clock Inputs
95
Figure 66 Fabric Clock Input
95
Figure 67 Clock Options
96
Figure 68 Spread Spectrum Clock Generation Enable
96
Figure 69 Spread Spectrum Modulation Options
96
Figure 70 Enable Dynamic Reconfiguration Interface
97
Table 28 Spread Spectrum
97
Figure 71 CLK_125 GUI
98
Figure 72 Transceiver Interface Selection from Catalog
98
Transceiver Interface Configurator
98
Figure 73 Transceiver Interface Configuration GUI
99
Table 29 Transceiver Interface General Settings
99
Table 30 Transceiver Interface PMA Settings
99
Table 31 Transceiver Interface PCS Settings
100
Table 32 Clocks and Resets
101
Figure 74 PMA Mode-Enable CDR Bit-Slip Port
102
Figure 75 XCVR Component with CDR Bit-Slip Port Enabled
102
Figure 76 XCVR Component with BMR Port Enabled
102
Figure 77 XCVR Component with DRI Port Enabled
103
Figure 78 Transceiver with ERM Example Smartdesign Component
103
Figure 79 PMA Only PCS Example Smartdesign Component
104
Figure 80 8B10B PCS Example Smartdesign Component
104
Figure 81 64B66B PCS Example Smartdesign Component
104
Figure 82 Soft PIPE PCS Example Smartdesign Component
105
Figure 83 Completed Transceiver Subsystem
105
Transceiver Modes
106
Full-Duplex Mode
106
Figure 84 Completed Transceiver Subsystem with ERM
106
Figure 85 Transceiver Modes Shown in Transceiver GUI
106
Half-Duplex Mode
107
Table 33 PCS Modes Supported
107
Libero Generated Files
108
Design Constraints
108
Timing Constraints
108
Figure 86 Derive Constraints Using Constraints Editor
109
Physical Constraints
110
Table 34 Physical Constraint Instances for XCVR
110
Adding Physical Constraints Using Libero
111
Invoking the Pin Planner
112
Figure 87 IO Editor GUI
112
Figure 88 XCVR Placement Tab
113
Figure 89 XCVR Signal Integrity Tab
113
Transceiver Initialization
114
Transceiver Initialization Data
114
5 Signal Integrity Conditioning
115
Figure 90 Signal Integrity Conditioning Flow
115
Transmitter
116
Transmit Emphasis and DC Amplitude
116
Impedance (Differential)
116
Tx Insertion Loss
116
Transmit Common Mode Level
116
Table 35 Amplitude and Emphasis
116
Receiver
117
Rx Insertion Loss
117
Rx CTLE
117
Rx Termination
117
AC/DC Coupled Connection
117
Loss-Of-Signal Detector
118
Polarity Invert
118
IO Editor for Signal Integrity
118
Table 36 LOS Range
118
Figure 91 IO Editor-XCVR View
119
Figure 92 IO Editor-Signal Integrity View
119
IO Editor-Signal Integrity
119
PDC Constraint File Commands for XCVR Signal Integrity
119
Table 37 TX Attributes and Values
120
Table 38 RX Attributes and Values
121
Smartdebug Signal Integrity
123
Figure 93 Smartdebug Signal Integrity GUI Panel
123
Figure 94 Loopback Modes-Far-End Example
124
Loopback Modes
124
Smartbert
124
Eye Monitoring
125
Figure 95 PRBS Self Test Near-End Loopback Example
125
Figure 96 Test Status Indicators
125
Figure 97 Eye Monitor Plot
126
Figure 98 Example of Optimize DFE
127
6 Simulation
128
RTL Simulation Mode
128
Figure 99 RTL Simulation Block Diagram
128
7 Debug and Testing
129
PRBS Generator/Checker
129
Loopback
129
EQ Far-End Loopback
129
EQ Near-End Loopback
129
CDR Far-End Loopback
129
Figure 100 Transceiver Loopbacks
130
Dynamic Reconfiguration Interface
131
Figure 101 PF_DRI Example
131
8 Board Design Recommendations
132
Transceiver Top-Level Pin out
132
Table 39 Transceiver Device Level Pin List
132
Design for Protocols
134
PCI Express
134
Figure 102 Connectivity between XCVR Interface and Pcie Edge Connector
134
Jesd204B
135
Interface
135
Figure 103 Connectivity between Polarfire Device and JESD204B Interface
135
Figure 104 Connectivity between Polarfire Device to SFP+ Interface
135
Unused Transceiver Pins
136
Transceivers Insertion Loss
136
Table 40 Transceivers Insertion Loss
136
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