Sony MDS-JA50ES Service Manual page 72

• IC207 Sampling Rate Converter, Digital Filter (MSM9404AGS-BX)/DIG board
Pin No. Pin Name
DO
1
SEL
2
SRDT
3
SWDT
4
5 SCK
XLAT
6
INIT
7
NC
8
VDD
9
10 NC
RBPH
11
12 STA
FRS
13
FRM
14
15 SLAVE
TEST5
16
17 TB7
MDO0
18
MDO1
19
MUTE
20
DATAO
21
22 BCKO
LRCKO
23
TEST4
24
GND
25
XI
26
27 GND
XO
28
29 XOO
VDD
30
NC
31
TB6 to TB4
32 to 34
MAO0
35
36 MAO1
ALRKO
37
ABCKO
38
NC
39
VDD
40
I/O
O Data output (Not used)
I Data select control input "L":DI0 n DO, "H":DI1 n DO (Fixed at "L")
O Serial data output
I Serial data input
I Serial clock input
I Serial latch pulse input
I Initialize input "L":Reset
— Not used
— Power supply (+3.3V)
— Not used
O Ring buffer R/W phase control monitor signal output "L":Control OFF (Not used)
Fs conversion rate measurement state monitor signal output "L":High accuracy
O
"H":High speed response mode (Not used)
Input/output Fs rate measurement time selection input
I
"L":High accuracy "H":High speed response mode (Fixed at "L")
Input/output Fs rate measurement mode signal input
I
"L":Automatic, "H":Manual (Fixed at "L")
I Output sync mode selection input "L":Slave, "H":Master (Fixed at "L")
I
Test pin (Fixed at "L")
I/O Test bus input/output (Open)
I
Data output serial data format setting input (Fixed at "L")
I
I Output mute setting input "L":Muted (DATAO only)
O
Data output (Fso output)
I/O Data output bit clock input/output
I/O Data output Fso word clock input/output
I Test pin (Fixed at "L")
— Ground
I
512 Fso output line master clock input
— Ground
O Clock output
O Output line master clock output (Not used)
— Power supply (+3.3V)
—
Not used
I/O Test bus input/output (Open)
I
D/A output serial data format setting input (Fixed at "L")
I
O D/A output word clock output Data changes at "L"n"H" edge (Not used)
O D/A output bit clock output Data changes at "L"n"H" edge (Not used)
— Not used
— Power supply (+3.3V)
— 94 —
Function