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Technical Details
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Figure 3-5. Interrupt Status Bits.
INT
Or of all Unmasked Int Status Bits
CPT
Command Pass Through.
APT
Address Pass Through.
DET
Device Trigger.
END
End (END or EOS Message Received).
DEC
Device Clear.
ERR
Error.
DO
Data Out.
DI
Data In.
SRQI
Service Request Input.
LOKC
Lockout Change.
REMC
Remote Change.
ADSC
Address Status Change.
CO
Command Output.
The 13 factors that can generate an interrupt have their
own status bit and mask bit. The interrupt status bits are always
set to one if the interrupt condition is met. The interrupt mask
bits decide whether the INT bit and the TLC interrupt pin will
be active for that condition.
___________________ _
SRQ Service ReQuest.
There is an SRQ input interrupt flag in bit6 of the interrupt
status register 2. This register can only detect a low going pulse
on the SRQ line, NOT its current. By catching each and every
transition the current state is known.
The SN75162 only allows SRQ receive when the computer
is acting as the system controller, ie ALL THE TIME in normal
use.
An IRQ to interrupt the processor can be generated by
SRQ transitions by appropriate setting of SRQI.
The Auxiliary Mode Register.
_________________________ _
The aux mode register controls many of the most powerful
features of the 7210 TLC. It allows it to take control and
become the active controller, it allows it to be the system
Chapter 3
PC Elite Reference
3-29
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