Power Up Faults - Nokia NPC-1 Series Troubleshooting Instructions

NPC-1
Troubleshooting Instructions
8 Infrared

Power up faults

Power up sequence
1 The UEM acts as a HW master during start up
• Vbatt limits: 2.1V for internal state machine, 3V triggering whole startup
• Regulator sequencing
• HW "core" regulators "on": Vio, Vcore, VR3, Vflash1
• These regulators supply the processors, memory, chip interfaces and
• Reset releasing delay
• Supply voltages stabilize to their UEM HW default values
• RFCLK grows to full swing
• The core is ready to run but waiting for the PURX release
• Reset releasing
• The UPP releases the SLEEPX up to the "non sleep" -state to prevent the
2 MCU starts running the Bootsrap Code
• written in stone/ UPP internal ROM
• the program checks if there is any reason for the FDL mode (Flash Down
• If there is an executable code in FLASH and there is no reason for FDL,
3 MCU runs the FLASH MCU code
• the phone initialization, user interfaces, internal blocks etc.
• Core regulator voltage setting for required DSP speed
• Initializes the DSP and concerning HW
• Releases DSP reset -> DSP starts running
Page 6
clock source in RF
UEM switching the regulators "OFF"
Load)
the MCU starts running the MCU program from FLASH.
ãNokia Corporation
PAMS Technical Documentation
Issue 1 10/01