Fig 18 An Xor Comparison Of The Data Indicates More Equal Bits; Fig 19 An Xor Comparison Indicates More Unequal Bits - Nokia RH-9 Series Ccs Technical Documentation

RH-9
System Module & UI
hardware interaction before locking can be changed (protects infrequently changed code
blocks). For this purpose, a dedicated pin called WP# is used. The WP signal is only con-
trolled by the hardware.
Lock block
The block's default power-up or reset status is locked. Locked blocks are fully protected
from alteration. Attempted program or erase operations to a locked block will return an
error in a status register inside the flash. A locked block's status can be changed to
unlocked or lock-down using the appropriate software commands. Writing the "Lock
block command" sequence can lock an unlocked block.
Unlock block
Unlocked blocks can be programmed or erased. All unlocked blocks return to the locked
state when the phone is powered down. An unlocked block's status can be changed to
the locked or locked-down state using the appropriate software commands. A locked
block can be unlocked by writing a "unlock block command" sequence, if the block is not
locked-down.
Lock-down block
Locked-down blocks are protected from program and erase operations (just like locked
blocks), but software commands alone cannot change their protection status. A locked-
down block can only be unlocked when the WP# signal is high. When the WP-signal
goes low, all locked-down blocks revert to locked. A locked or unlocked block can be
locked-down by writing a "Lock-Down Block command" sequence. Locked-down blocks
revert to the locked state at device reset or power-down.
AMD
All blocks have a locking latch and upon power up all blocks are locked. To unlock a
block, a command sequence must be written. Once the unlock command sequence is
written the SW can unlock as many blocks as required by entering the block address
while keeping a specific address high. If the address is taken to low, the block will be
locked instead of unlocked. The SW locking is similar to the Intel SW locking.
The AMD flash also has the same hardware lock as Intel. The blocks are locked if WP# is
set to low. If the WP# signal is driven high, the SW can control the locking of the blocks.
Finally, if the V
Memory Operation
Read
The flash allows asynchronous random access read and synchronous burst read.
CE# - low selects the device and puts it in asynchronous read mode. For all read modes,
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pin is set to low all blocks are locked.
PP
ãNokia Corporation
CCS Technical Documentation
Issue 1 11/02