NAD T748 Service Manual page 14

IC BLOCK DIAGRAMS & PIN DESCRIPTION
IC101 : STM32F103ZET6 (FLASH MCU)
IC BLOCK DIAGRAMS
TRACECLK
TRACED[0:3]
as AS
NJTRST
JTDI
JTCK/SWCLK
JTMS/SWDIO
JTDO
as AF
A[25:0]
D[15:0]
CLK
NOE
NWE
NE[4:1]
NBL[1:0]
NWAIT
NL (or NADV)
as AF
D[7:0]
CMD
CK as AF
112AF
PA[15:0]
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
PF[15:0]
PG[15:0]
4 channels
3 compl. channels
BKIN, ETR as AF
4 channels
3 compl. channels
BKIN, ETR as AF
MOSI, MISO,
SCK, NSS as AF
RX, TX, CTS,
RTS, CK as AF
8 ADC123_INs
common to the 3 ADCs
8 ADC12_INs common
to ADC1 & ADC2
5 ADC3_INs on ADC3
V
REF–
V
REF+
TPIU
Trace/trig Trace
Pbus
SW/JTAG
controller
Ibus
Cortex-M3 CPU
Dbus
F max : 48/72 MHz
System
NVIC
GP DMA1
7 channels
GP DMA2
5 channels
FSMC
SDIO
AHB2
APB2
EXT.IT
WKUP
GPIO port A
GPIO port B
GPIO port C
GPIO port D
GPIO port E
GPIO port F
GPIO port G
TIM1
TIM8
SPI1
USART1
Temp. sensor
12-bit ADC1 IF
12-bit ADC2 IF
12-bit ADC3 IF
@ V DDA
V DD
Flash 512 Kbytes
64 bit
POR
Reset
SRAM
@V DDA
64 KB
Int
RC 8 MHz
RC 40 kHz
PLL
PCLK1
Reset &
PCLK2
Clock
HCLK
control
FCLK
Backup interface
AHB2
APB1
2x(8x16b
2x(8x16b
SRAM 512 B
WWDG
TIM6
TIM7
2-2
@V DD
Power
Volt. reg.
V SS
3.3 V to 1.8 V
@V DDA
Supply
NRST
supervision
V DDA
POR / PDR
V SSA
PVD
@V DD
OSC_IN
XTAL OSC
OSC_OUT
4-16 MHz
IWDG
Standby
interface
V BAT =1.8 V to 3.6 V
@ V BAT
OSC32_IN
XTAL32kHz
OSC32_OUT
Backup
TAMPER-RTC/
RTC
reg
AWU ALARM/SECOND OUT
4 channels, ETR as AF
TIM2
4 channels, ETR as AF
TIM3
TIM4 4 channels, ETR as AF
TIM5 4 channels as AF
RX, TX , CTS, RTS,
USART2
CK as AF
RX, TX, CTS, RTS,
USART3
CK as AF
RX,TX as AF
UART4
RX,TX as AF
UART5
MOSI/SD, MISO
SPI2 / I2S2
it)
SCK/CK, MCK, NSS/WS as AF
MOSI/SD, MISO
SPI3 / I2S3
it)
SCK/CK, MCK, NSS/WS as AF
I2C1
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
I2C2
bxCAN device
USBDP/CAN_TX
USBDM/CAN_RX
USB 2.0 FS
device
DAC_OUT1 as AF
12bit DAC1
IF IF
IF
DAC_OUT2 as AF
12bit DAC 2
@V DDA
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