Timing Tests - Atari 520STE Field Service Manual

3.13.2 DMA Sound
Connect an oscilloscope at the stereo output jacks. The setting should be 1
ms/division, 5 volts/division. There are four parts to this test. After observing the
signals, proceed to the next part by pressing the space bar. In each case, the output
signal amplitude should go from 0 volts to maximum amplitude in steps.
a. Mono 1 kHz: Both channels output the same signal; it should approximate a
sine wave and be 5–6 volts in amplitude.
b. Stereo 1 kHz/500 Hz: Verify that the right and left channels have correct
frequencies. As one channel increases in amplitude, the other channel
decreases. Maximum amplitude is 5–6 volts.
c. Treble: A 12.5 kHz signal is output on both channels. Maximum amplitude is
about 6 volts.
d. Bass: A 50 Hz signal is output on both channels. Maximum amplitude is about
6 volts.
3.14 TIMING TESTS (T)
These tests are run at power–up as well as being selectable from the menu. The
MFP timers, the GSTMCU timing for VSYNC and HSYNC, and the Memory
Controller video display counters are tested. The video display test redirects display
memory throughout RAM and verifies that the correct addresses are generated. Odd
patterns may flash on screen as this test is run. There are two tests which check the
bus timing for the 1772 and PSG chips. An error message is printed on the screen
then the test is run. If the test passes, the message is erased. If not, a Bus Error will
occur and the message will remain. If a terminal is connected to the RS232 port, the
message will not be erased, but "Pass" will be printed.
3.14.1 Timing Test Error Codes
T0 MFP Timer Error. One or more of the four timers in the MFP did not generate
an interrupt on counting down.
T1 Vertical sync. GSTMCU is not generating vertical sync in the required time
period.
T2 Horizontal Sync. GSTMCU is not generating horizontal sync in the required
time period.
T3 DispIay Enable. GSTMCU is not generating DE output or the MFP is not
generating an interrupt.
T4 Video Counter Error. The memory controller is not generating the correct
addresses for the display. This will result in a broken–up display in some or all
display modes.
T5 PSG Bus Error. The PSG chip is defective.
T6 1772 Bus Error. The 1772 chip is defective.
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