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MAIN ( 2D DIGITAL ) SCHEMATIC DIAGRAM
0 3 MAIN(2D DIGITAL)
5
4
I2C_DATA_AV
I2C_CLK_AV
3
LC1201
100µ
SW5V
GND
2
C_FROM_DIGI
GND
Y_FROM_DIGI
GND
V/Y_TO_DIGI
GND
C_TO_DIGI
KILLER_DET
Fsc
GND
1
A
R1203
220
R1204
220
Q1201
2SC1317/RS/
R1201
R1202
120
100
C1246
C1243
0.01
47
/6.3
C1201
47
/6.3
D1201
RD4.3ES/B3/
C1244
4.7
/50
C1208
OPEN
R1205
1k
R1206
560
L1201
C1210
OPEN
OPEN
B
C
C1212
0.001
C1211
47
/6.3
R1207
5.6k
L1202
R1208
100µ
12k
IC1201
JCP8036
C1215
47
/6.3
L1203
100µ
IIC_DATA
IIC_CLK
RESET
CMUTE
VSS
C1217
0.1
VDD
R1210
39k
C1218
±0.5%
0.1
VREF
COUT
R1211
R1221
15k
OPEN
±0.5%
IOB
C1219
1
COMP
YOUT
L1204
100µ
R1214
R1217
R1218
180
150
300
C1220
±0.5%
±0.5%
47
/6.3
R1212
1k
L1205
2.7µ
C1223
Q1202
R1213
C1222
68p
180
150p
R1215
1k
L1206
2.7µ
R1220
560
C1226
Q1203
R1216
C1225
68p
150
150p
D
E
2-11
2-12
C1216
0.1
NC( TEST)
NC( TEST)
NC( TEST)
C1237
0.1
FSC_IN
VDD
VSS
NC( TEST)
NC( TEST)
NC( TEST)
NC( TEST)
AVDD
C1234
0.1
R1224
560
C1229
0.01
C1228
Q1205
4.7
/50
2SC4081/S/
L1208
15µ
Q1204
C1238
18p
C1245
C1239
15p
56p
R1222
470
F
C1236
0.1
L1207
100µ
C1235
47
/6.3
p20312001a_rev0
G
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