Mitsubishi Electric MELSEC QJ71PB92D User Manual page 34

Programmable logic controllers, profibus-dp interface modules
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3 SPECIFICATIONS
3 - 19
(3) Address information area (Buffer memory address: 1920 (780
2039 (7F7
))
H
This area shows the station address, input byte length, and output byte length for
each slave station. This allocation is set by the GX Configrator-DP. The station
addresses for the 1st through the 60th stations are stored in the order of
registration in the GX Configrator-DP. (Station addresses: 1 to 126, do not need
to be sequential numbers.)
The address information area configuration is shown below. For details refer to
Section 3.4.2 (4).
Buffer memory
address demical
(Hexadecimal)
1920(780
)
H
1st station input byte length
1921(781
)
H
1922(782
)
H
2nd station input byte length
1923(783
)
H
n th station input byte length
2036(7F4
)
H
59th station input byte length
2037(7F5
)
H
2038(7F6
)
H
60th station input byte length
2039(7F7
)
H
(a) The station address of unallocated stations is FFFF
FF
.
H
(b) When the I/O byte length of allocated stations is 0, a 0 is stored for the byte
length.
(c) The n does not show the station address but represents a number (the nth
number) used for the input/output area.
Station address of 1st station
1st station output byte length
Station address of 2nd station
2nd station output byte length
Station address of n station
n th station output byte length
Station address of 59th station
59th station output byte length
Station address of 60th station
60th station output byte length
MELSEC-Q
) to
H
, and the I/O byte is
H
3 - 19

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