Sony UP-960 Service Manual page 56

IC
HA11465A (HITACHI)
NTSC COLOR TV VIDEO AMPLIFIER
—TOP VIEW—
16 15 14 13 12 11
V
CC
17 1 2 3 4 5 6
CHROMA AP
OUT IN
14 12
VIDEO VIDEO
15
VIDEO
IN BUFFER CONTROL
NOISE SYNC
16
SYNC
IN CANCEL SEPARATOR
1
SYNC SYNC
SEP
(1)
AP : APERTURE
BLK : BLANKING
BRT : BRIGHTNESS
CNTR : CONTRAST
CONT : CONTROL
SYNC SEP : SYNCHRONIZATION PULSE SEPARATION
V.AMP : VIDEO AMPLIFIER
HD14053BFP (HITACHI)FLAT PACKAGE
MC14053BF-T2
C-MOS TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
—TOP VIEW—
X1 1 V 16
I/O DD
X0 2 15 XC
I/O I/O
Y1 3 14 ZC
I/O I/O
YC 4 13 Z1
I/O I/O
Y0 5 12 Z0
I/O I/O
EN
6 11 AZ
IN I/O
7 V 10 AX
EE I/O
8 GND 9 AY
I/O
6-4
10 9
GND
7 8 18
CNTR CNTR
AP CNTR OUT OUT V.AMP
CONT CONT (1) (2) IN
13 11 10 9 7
CONTRAST VIDEO
CONTROL AMP
PEDESTAL
BLANKING
CLAMP
2 3 6 4 5
SYNC BRT BLK BLK
SEP OUT CONT IN IN
(2)
2 X0
1 X1 XC 15
OPEN
10 AX
5 Y0
3 Y1 YC 4
OPEN
9 AY
12 Z0
13 Z1 ZC 14
OPEN
11 AZ
EN V
EE
6 7
CONT. INPUTS
ON
CHANNEL
EN A (X, Y, Z)
0 0 0
0 : LOW LEVEL
0 1 1
1 : HIGH LEVEL
1 x OPEN
x : DON'T CARE
HD6473042F12 (HITACHI)
C-MOS 16-BIT MICRO PROCESSOR
—TOP VIEW—
76 A-V
DD
80
85
A-GND
90
GND
95
8
VIDEO
OUT
100
PIN PIN
I/O SIGNAL I/O
No. No.
1 — V 26 I/O
DD
2 I/O PB0/TIOCA3/TP8 27 I/O
3 I/O PB1/TIOCB3/TP9 28 I/O
4 I/O PB2/TIOCA4/TP10 29 I/O
5 I/O PB3/TIOCB4/TP11 30 I/O
6 I/O PB4/TOCXA4/TP12 31 I/O
7 I/O PB5/TOCXB4/TP13 32 I/O
DREQ0
8 I/O PB6/ /TP14 33 I/O
ADTRG DREQ1
9 I/O 34 I/O
PB7/ / /TP15
RESO
10 O 35 —
11 — GND 36 I/O
12 I/O P90/TXD0 37 I/O
13 I/O P91/TXD1 38 I/O
14 I/O P92/RXD0 39 I/O
15 I/O P93RXD1 40 I/O
IRQ4
16 I/O P94/ /SCK0 41 I/O
IRQ5
17 I/O P95/ /SCK1 42 I/O
18 I/O P40/D0 43 I/O
19 I/O P41/D1 44 —
20 I/O P42/D2 45 I/O
21 I/O P43/D3 46 I/O
22 — GND 47 I/O
23 I/O P44/D4 48 I/O
24 I/O P45/D5 49 I/O
25 I/O P46/D6 50 I/O
75
MD2
74
MD1
73
MD0
66
EXTAL
67
XTAL
61
ø
62
STBY
63
RES
10
RESO
64
NMI
72
P66/LWR
71
P65/HWR
70
P64/RD
69
P63/AS
60
P62/BACK
59
P61/BREQ
58
P60/WAIT
91
P84/CS0
90
P83/CS1/IRQ3
89
P82/CS2/IRQ2
88
P81/CS3/IRQ1
87
P80/RFSH/IRQ0
PORT B
50
45
GND
40
V 35
DD
30
26
PIN PIN
SIGNAL I/O SIGNAL I/O
No. No.
P47/D7 51 I/O P26/A14 76 —
P30/D8 52 I/O P27/A15 77 I
P31/D9 56 I/O P50/A16 78 I
P32/D10 54 I/O P51/A17 79 I
P33/D11 55 I/O P52/A18 80 I
P34/D12 56 I/O P53/A19 81 I
P35/D13 57 — GND 82 I
WAIT
P36/D14 58 I/O P60/ 83 I
BREQ
P37/D15 59 I/O P61/ 84 I/O
BACK
V 60 I/O P62/ 85 I/O
DD
P10/A0 61 O 86 —
Ø
STBY
P11/A1 62 I 87 I/O P80/
RES
P12/A2 63 I 88 I/O P81/
P13/A3 64 I NMI 89 I/O P82/
P14/A4 65 — GND 90 I/O P83/
P15/A5 66 I EXTAL 91 I/O
P16/A6 67 I XTAL 92 —
P17/A7 68 — V 93 I/O
DD PA0/TP0/
AS
GND 69 I/O P63/ 94 I/O
PA1/TP1/
RD
P20/A8 70 I/O P64/ 95 I/O
PA2/TP2/TIOCA0/TCLKC
HWR
P21/A9 71 I/O P65/ 96 I/O
PA3/TP3/TIOCB0/TCLKD
LWR
P22/A10 72 I/O P66/ 97 I/O PA4/TP4/TIOCA1/A23
P23/A11 73 I MD0 98 I/O PA5/TP5/TIOCB1/A22
P24/A12 74 I MD1 99 I/O PA6/TP6/TIOCA2/A21
P25/A13 75 I MD2 100 I/O PA7/TP7/TIOCB2/A20
PORT 3 PORT 4
ADDRESS BUS
DATA BUS (MSB)
DATA BUS (LSB)
CLOCK
H8/300H CPU
OSC.
INTERRUPT
CONTROLLER
DMA
CONTROLLER
MASK
ROM
REFRESH
CONTROLLER
RAM
WATCH DOG
TIMER
16-BIT
SERIAL
INTEGRATED
COMMUNICATION
TIMER VALSE
INTERFACE
UNIT
x 2CH
PROGRAMMABLE
A/D CONVERTER
TIMING
D/A CONVERTER
PATTERN
CONTROLLER
PORT A PORT 7
SIGNAL
A-V
DD
VREF
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6/DA0
P77/AN7/DA1
A-GND
RFSH IRQ0
/
CS3 RAS IRQ1
/ /
CS2 IRQ2
/
CS1 IRQ3
/
CS0
P84/
GND
TEND0
/TCLKA
TEND1
/TCLKB
56
A19/P53
55
A18/P52
54
A17/P51
53
A16/P50
52
A15/P27
51
A14/P26
50
A13/P25
49
A12/P24
48
A11/P23
47
A10/P22
46
A9/P21
45
A8/P20
43
A7/P17
42
A6/P16
41
A5/P15
40
A4/P14
39
A3/P13
38
A2/P12
37
A1/P11
36
A0/P10
17
P95/SCK1/IRQ5
16
P94/SCK0/IRQ4
15
P93/RXD1
14
P92/RXD0
13
P91/TXD1
12
P90/TXD0
UP-960(UC)
UP-960CE(CE)