Tektronix 1502C Service Manual page 105

Circuit Descriptions
CPU and Display Memory
Interface
5–38
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
There are two data buses and two address buses on the controller. The first data bus,
DB7 – DB0, is used to access registers internal to the controller. These internal
registers are used to initialize the controller.
The second data bus, RD7 – RD0, is used to read bit pattern data from the display
memory. The data bus from the display memory is tied directly to the RD7 – RD0
data bus, and indirectly through a bidirectional bus transceiver, U1050, to the DB7
– DB0 data bus. The DB7 – DB0 data bus is tied directly to the CPU data bus through
the 40-pin connector.
The first address bus, MA12 – MA0, is tied to the display memory and addresses
it. MA12 – MA0 can have one of two sources. The first is an internal address in the
controller, which is the address of the currently accessed bit pattern data byte. The
second is the address resent on the second address bus, A11 – A0.
This second address bus is tied to the CPU address bus through the 40-pin connector
and is used to address the display memory during the time the CPU is updating the
display memory.
The control signal DIEN controls the multiplexing of the internal address and A11
– A0 to MA12 – MA0. A15 – A12 are tied low.
There are several other relevant control signals to the controller: CS <chip select>,
WR <write>, and RD <read>.
CS and WR are used in conjunction with A0 to write to the internal registers. CS
and RD in conjunction with A0 to read them.
XT is the system clock, from which all timing in the controller is derived. It is
supplied via the 40-pin connector at 0.625 MHz.
DRAM <display memory select> is used with WR by the CPU to select and write
to the display memory. DRAM and RD are used to read.
The combinational logic associated with the selection of the display memory is such
that the memory is set to the selected read mode at all times except when the CPU
accesses it. In that case, it could be either selected read or selected write at the
discretion of the CPU. This combinational logic also controls the flow of data
through the transceiver.
1502C MTDR Service Manual