Sony XDP-PK1000 Service Manual page 26

XDP-PK1000
Pin No. Pin Name
59 DAO4 (R_L-CH)
60 DVDD5
61 DAO5 (SUB-CH)
62 DVSS5
63 VDD1-3
64 VSS-2
65 XVSS3
66 XI
67 XO
68 XVDD3
69 ADVDD3
70 ADIN1 (IN_L-CH)
71 ADVREFL
72 ADVCM
73 ADVREFH
74 ADIN2 (IN_R-CH)
75 ADVSS3
76 MS
77, 78 BUS0, BUS1
79 BUS2/So
80 BUS3/Si
81 BUCK/SCL
82 /CCE
83 VDD3-2
84 VSS-3
85 /RST
86 VDD1-4
87 DEC_REQ
88 BSIF-REQ
89 BSIF-GATE
90 BSIF_DATA
91 BSIF_BCK
92 BSIF_LRCK
93 DEC_XMUTE
94 ZDET
95 CD-MON0/SP_DATA
96 CD-MON1/SP_CLK
97 TEST
98 PDO
99 TMAX
100 LPFN
26
I/O
O Rear L-channel data output terminal
- Power supply terminal (+3.3V)
O Sub channel data output terminal
- Ground terminal
- Power supply terminal (+1.5V)
- Ground terminal
- Ground terminal
I System clock input terminal (16.934 MHz)
O System clock output terminal (16.934 MHz)
- Power supply terminal (+3.3V)
- Power supply terminal (+3.3V)
I Audio signal (L-channel) input terminal
O Reference voltage (+1.65V) output terminal
O Reference voltage (+1.65V) output terminal
O Reference voltage (+1.65V) output terminal
I Audio signal (R-channel) input terminal
- Ground terminal
I I/F mode selection signal input terminal
I/O Bus data input/output with the iPod/iPhone controller
I/O Bus data input/output with the iPod/iPhone controller
I/O Bus data input/output with the iPod/iPhone controller
I Bus clock signal input from the iPod/iPhone controller
I Chip enable signal input from the iPod/iPhone controller
- Power supply terminal (+3.3V)
- Ground terminal
I Reset signal input from the iPod/iPhone controller
- Power supply terminal (+1.5V)
O Request signal output to the iPod/iPhone controller
O Request signal output to the iPod/iPhone controller
I Gate signal input from the iPod/iPhone controller
I Audio data input from the iPod/iPhone controller
I Bit clock signal input from the iPod/iPhone controller
I L/R sampling clock signal input from the iPod/iPhone controller
I Muting on/off control signal input from the iPod/iPhone controller
O Zero detection signal output to the iPod/iPhone controller
O Spectrum analyzer data output terminal
I Spectrum analyzer data transfer clock signal input terminal
I Test mode setting signal input terminal
O Phase error margin signal between EFM signal and PLCK signal output terminal
O TMAX detection result output terminal
I Inverted signal input for PLL loop fi lter from the operation amplifi er
Description
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Fixed at "H" in this unit
"L": reset
Not used
Not used
Normally fi xed at "L"
Not used
"H": muting on
Not used
Not used