IBM 7090 Instruction-Reference page 45

4.2.02 Core Storage to CPU
When in automatic status, data flow from core storage to the CPU (Figure 4.1-2)
always occurs during I cycles and may occur during E cycles. In either case, the data
are routed to the multiplexor storage bus where they are gated to the CPU. Data trans-
mitted to the CPU during I cycles are in the format of instructions, whereas data trans-
mitted to the CPU during E cycles may be in any format.
Notice that the bus unconditionally feeds both banks of data channels. However, data
are gated through the channel input switches only during B cycles or the E cycle of a
reset and load or load channel instruction. The address field (21-35) of the bus also
feeds the multiplexor address switches. These positions are gated through the switches
only during a look-ahead address control operation.
I Cycle Flow
At 16(D3), data on the multiplexor storage bus are gated to the CPU. CPU storage
bus positions S, 1-35 are set to the storage register at 17(Dl), while positions S, 1-11
are routed to the instruction register. If the CPU storage bus positions 1 or 2 hold a
one at 18(Dl), bus positions S, 1, and 2 are set to instruction register positions S, 8,
and 9, respectively. If the CPU storage bus positions 1 or 2 do not hold a one at 18(Dl),
bus positions S, 3-11 are set to instruction register positions S, 1-9 respectively.
E Cycle Flow
During all E cycles in which store control is not up, the multiplexor storage bus is
gated to the CPU at E6(D3). At E7(Dl), positions S, 1-35 of the CPU storage bus are
set to the storage register.
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