Multiplexor Storage Bus - IBM 7090 Instruction-Reference

by gating the last half of the 1 clock trigger pulse with the negative portion of the odd
ring drive pulse. The rise of the Al(Dl) pulse turns on two clock trigger, and the turn-
ing on of the two clock trigger turns off zero clock trigger. This sequence continues
through 11 clock trigger. The rise of the All(Dl) pulse turns zero clock trigger on
again. The following chart shows the controls significant to each stage of the ring.
Clock
Tgr
o
1
2
3
4
5
6
7
8
9
10
11
Turned
on by
All(Dl)
AO(Dl)
Al(Dl)
A2(Dl)
A3(Dl)
A4(Dl)
A5(Dl)
A6(Dl)
A7(Dl)
A8(Dl)
A9(Dl)
AI0(Dl)
Turned off by
2 clock tgr
3 clock tgr
4 clock tgr
5 clock tgr
6 clock tgr
7 clock tgr
8 clock tgr
9 clock tgr
10 clock tgr
11 clock tgr
o
clock tgr
1 clock tgr
Duration
All(D2)
AO(D2)
Al(D2)
A2(D2)
A3(D2)
A4(D2)
A5(D2)
A6(D2)
A 7(D2)
A8(D2)
A9(D2)
AI0(D2)
Output
All(D2)
AO(D2)
Al(D2)
A2(D2)
A3(D2)
A4(D2)
A5(D2)
A6(D2)
A 7(D2)
A8(D2)
A9(D2)
AI0(D2)
Gated
Output
AO(Dl)
Al(Dl)
A2(Dl)
A3(Dl)
A4(Dl)
A5(Dl)
A6(Dl)
A 7(Dl)
A8(Dl)
A9(Dl)
AI0(Dl)
All(Dl)
Note that the pulse width of each clock trigger is twice that of an individual clock
pUlse. This slower switching of the clock triggers provides for increased reliability
in the operation of the clock.
The multiplexor clock pulse distribution enables the individual clock pulses to be
distributed to the CPU and data channels. Because of inherent delays in logic blocks,
clock pulses distributed to the CPU arrive about one clock pulse late. For this reason,
those clock pulses distributed from the multiplexor to the CPU are labeled one higher
than the actual clock pulse. Therefore, an AO(Dl) pulse going to the CPU would be
labeled Al(Dl). This pulse leaves the multiplexor at AO time but, when it arrives at
the CPU, the Al(Dl) pulse is rising at the multiplexor.
It
is important to notice that
Al(Dl) pulses at the CPU and multiplexor now are in coincidence, although developed
from different clock triggers. This provides for continuity in the timing relationship
between the CPU and multiplexor.
4.1.02 Multiplexor Storage Bus
The multiplexor storage bus (Figure 4.1-2) routes all data from core storage to
either the data channels or the CPU. Seventy-two lines from core storage feed the bus,
36 of which lines carry data at a given time. Lines 0-35 are logically OR'ed with lines
36-71, respectively.
The bus feeds a group of 36 AND circuits that act as inputs to the CPU. The bus also
feeds both banks of the data channel by way of the channel buses.
In a multiplexor storage bus test, positions 1-35 of the multiplexor storage bus feed
a matrix, which tests positions 1-35 and 3-17 for a zero condition. The zero test on
positions 3-17 is used in conjunction with the multiplexor look-ahead circuits. Zero
testing positions 1-35 provide for minimum execution time of various CPU instructions.
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