IBM 7090 Instruction-Reference page 43

~
CPU
Inst Reg
S,l-
-9
3.04.00.1
Multiplexor
Stg Bus to
CPU Stg Bus
1.00.01.1
1
~
AND
C;
1- 1111 - -~
T
i
CPU
Storage Reg
S,l-
-35
2.01.00.1
CPU
Memory Data
Register Out Sw's
0- -35136-
-71
1 1
Multiplexor
Storage Bus
S,l- -20
I
21- -35
I I l
+
,
-~
Channel Bus
Channel Bus
Multiplexor
A-D E - H
Address Sw's
S,l-
-35 S,l-
-35 3-
-17
2.05.10.1 2.05.10.1
3.06.22.1
~
! 1
Channel Channel
Channel Location
Input Switches Input Switches
Counter Sw's
$,1-
A-D
-35 S,l-
E-H
-35 3-
E-H
-17
60.26.01.1
60.26.01.1
60.10.13.1
Channel Location
Counter Switches
A-D
3-
-17
60.10.13.1
FIGURE 4.1-2. FLOW FROM MULTIPLEXOR TO CPU
AND DATA CHANNELS
Channel A-D
Channel E-H
Storage Register
Stg Bus Sw's
Stg Bus Sw's
S.l
-35
S,l- -35 S,l-
2.01.00.1 60.10.19.1
60.10.19.1
I
1
1
~
Multiplexor
Stg Bus OR'ing
2.05.22.1
1
Memory Data
Register in Sw's
0- -71
FIGURE 4.1-3. FLOW FROM CPU AND DATA CHANNELS
TO MULTIPLEXOR
42
I
-35
~
Memory
Address Register
3-
-17
1.02.00.1