8031 Reads From Memory; 8031 Writes To Memory; Dasp 8 Asic - Alesis MidiVerb 3 Service Manual

4.4.2 8031 Reads From Memory

8031 reads from memory begin as any normal read would. The 8031 sets up the address the
address buss (see section 4.1 for details) and presents it to the SRAM via U26 (A0-A7) and U15 (A8-
A10). If the address is memory map decoded by U17 to indicate access to the SRAM, it sets up a
chain of events. Diagram 4 shows the basic timing of these events. U18 (pins 4, 5, and 6) ensures
that the read assertion of the 8031 only passes through to the SRAM during the low half of DLYD
6MHZ (Diagram 4 SRAM OE). Latch U11 is output enabled as soon as 8031 ReaD is asserted, and
now controls the 8031 data buss. The actual data on the buss however, won't be valid until the
6MHZ line goes high (Diagram 4 U11 Data Valid). The latch ensures that data is good when the
8031 samples the buss (latches the contents of the buss into itself) even though the SRAM itself
may be busy with the ASIC.

4.4.3 8031 Writes to Memory

Writing to the SRAM from the 8031 is a little trickier. Diagram 5 shows the basic timing of
Diagram 5
6MHz clock switches the U16 to the A inputs. Since U16 switch 2A is tied high, the low signal to the
SRAM WE is removed (allowing the ASIC control again). Shortly after this, the DLYD 6MHZ line will
again go from high to low, resetting U20A and returning Q to it's normal state.

4.5 DASP 8 ASIC

The DASP (Digital Audio Signal Processor) 8 ASIC (Application Specific Integrated Circuit), is
a complex, LSI IC designed specifically to handle the specialized needs of digital effects processing.
Obviously, a full discussion of this device is beyond the scope of this manual, however, a brief
introduction to the device is definitely in order.
The DASP 8 contains a SAR (Successive Approximation Register), a writable control store
(internal memory for algorithm storage), and a RISC (Reduced Instruction Set Computer) for use as
an Arithmetic Logic Unit. Memory management hardware, and a variety of control hardware round
out the package. Some important control signals are outlined below.
these events. The process again begins as a normal
8031 write to memory. The address will be presented to
the SRAM when appropriate. The write assertion from
the 8031 will clock the data to be written into U12, but
U12 will not be output enabled until allowed by DLYD
6MHZ. The complications arise when actually asserting
the SRAM WE line. Observe that the WR WCS is not
only used to latch the data from the 8031 into U12, but it
is also sent to the D input of flip-flop U20A (pin 2).
Normally the Q output of this device is high (as it is
constantly being reset by DLYD 6MHZ), but when WR
WCS goes high, it will be clocked into the flip-flop with
the next low-high transition of DLYD 6MHZ (after a little
propagation delay provided by U15/switch 2). At this
point Q is low. This low signal then passes through U16
(pins 6 and 7) and on to the SRAM WE. This however
doesn't last long, as the next high-low transition of the