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compared. This process continues until a value is found for all 16 bits, and the data is ready for
further processing by the ASIC. In order to see these signals properly on the scope, it will be
necessary to use an external scope sync (use U6, pin 9 as the sync source). Diagrams 2, and 3,
show the DAC output during a single SAR cycle, with no input, and full input.
4.0 DIGITAL SIGNAL PATHS
The digital portion of the M3 is somewhat complex, incorporating 2 data and address busses,
as well as the control circuitry necessary for intercommunication.
4.1 80C31 MICRO CONTROLLER CIRCUIT
The 80C31 MPU controls all "user interface" functions of the M3. These functions range from
handling the front panel buttons, to continuously updating algorithm information to the DASP 8 ASIC.
Note that the 8031 data buss serves a dual purpose. This buss multiplexes between low order
addresses (1st 8 bits), and data. Latch U26 is used to hold the low order address half, during 8031
read and write cycles. The EPROM (U25) is used to hold both program information, and algorithm
data. The E 2 PROM (U24) holds system variables, as well as user preset data. MIDI I/O is handled
through the 8031's built in RXD (Read Serial Data), and TXD (Transmit Serial Data) ports. Front
panel keypad decoding is handled through a combination of memory mapped I/O (see section 4.3),
and the 8031's built in I/O ports.
4.2 RESET
The 8031 reset circuit is perhaps the single most important circuit in the M3. When this circuit
is functioning incorrectly, a complete lock-up of the machine, will occur. A thorough knowledge of the
operation of this circuit will greatly facilitate troubleshooting this unit. Note that the first units released
did not incorporate the full reset circuit described below. These units used a simple resistor/capacitor
circuit, and would occasionally fail to reset (particularly if the unit was turned off, and then back on
rapidly). Most of these early units have been retrofitted with an extra board containing the newer
reset circuit. The newest board revisions incorporate the reset on the board.
On power up, the 2N4401 transistor is off (the raw supply hasn't raised up far enough yet to
bias the transistor on, through R202, R203, and the zener divider network). C100 is allowed to
charge to +5V via R201 and the 1N914 signal diode. When the raw supply reaches approximately 7
volts, the transistor will turn on, discharging C100 through R200, and dropping the reset line low.
4.3 MEMORY MAPPED I/O
The M3 utilizes a memory mapped I/O system in order to deal with the wide variety of
functions that the 8031 needs to access. During write cycles of the 8031, data on the 8031 data buss
is made available to a series of latches (U12, U22, and U23). When A15 (address's most significant
bit) is active, the 3 to 8 line demux (U35) is used to decode several other significant address lines,
and send a strobe to the clock input of one of these latches. Consequently, data can be "stored" into
a latch simply by writing a value into a nonexistent memory location. Memory mapped input works
much the same. The address lines are again decoded when A15 is active. This time however,
instead of strobing a clock line, the output enable of the selected latch is strobed, placing it's
information on the data buss. The 8031 can then read the data for use as necessary.
4.4 WRITABLE CONTROL STORE
The writable control store is definitely the most complex circuit in the M3. The purpose of this
circuit is to act as a mutually accessible (8031 and DASP 8) storage area for the DASP 8 "control"
programs. This allows the 8031 to manipulate algorithms in real-time. Because the two devices
operate asychronously a great deal of control logic is necessary to prevent buss conflicts. Timing is
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