Ms Board Schematic (5 Of 18) - Sony NSZ-GS7 Service Manual

MS BOARD SCHEMATIC (5 OF 18)

1 | 2 | 3
R6008 NC_4.7K_J
3,8 BG2_NAND_CE1#
socJtagFromSM
0: Separate soc JTAG
1: socJtagFromSM
Default:1
A
VD_3P30
R6004 NC_4.7K_J
R6009 4.7K_J
4 STRP_SYSPLLBYPS
—
sysPllByps
0: Do not bypass sys PLL
1: Bypass sys PLL
Default:0
VD_3P30
R6005 NC_4.7K_J
B
R6010 4.7K_J
4 STRP_MEMPLLBYPS
memPllByps
0: Do not bypass mem PLL
1: Bypass mem PLL
Default:0
—
VD_3P30
R6006 4.7K_J
R6011 NC_4.7K_J
3 STRP_SOC_TDO_OEN
software_strap[6]
Used to enable/disable SOC_TDO OEN:
C
0: to enable OEN when pin is used for SOC TDO
1: to disable OEN,pin is used for other fuction
Default:1
VD_3P30
R6007 NC_4.7K_J
—
R6012 4.7K_J
3 BG2_NAND_CE0# software_strap[5]
Used by HW as cpu1PllByps
0: Do not bypass CPU1 PLL
1: Bypass CPU1 PLL
Default:0
D
—
VD_3P30
R6000 NC_4.7K_J
E
2 JTAG_SEL0
R6001 NC_4.7K_J
2 JTAG_SEL1
—
SM_JTAG_SEL[1:0]==00 && ENG_EN==1 ARM ICE for CPU 2 and 0 and 1 (SOC should NOT be power down)
SM_JTAG_SEL[1:0]==00 && ENG_EN==0 ARM ICE for CPU 2 and 0. (CPU 1 bypassed) (SOC should NOT be power down)
SM_JTAG_SEL[1:0]==10 JTAG Boundary scan for SOC and SM
SM_JTAG_SEL[1:0]==11 Reserved
VD_3P30
F
R6002 NC_4.7K_J
2 TEST_EN
TEST enable
— SM_TEST_EN ==1 for the following modes:
1 : enable scan or AC scan testes
SM_JTAG_SEL[0] is scan enable
0: enable ARM ICE JTAG connections
SM_JTAG_SEL[1] is scan compression enable
VD_3P30
R6003 4.7K_J
G
3 BG2_ENG_EN
Engineering debug feature enable bonding option,
tie to VIO6(3.3V Fixed) to enable debug features
—
H
—
I
NSZ-GS7/NSZ-GX70
—
| 4 | 5 | 6 |
R6027 47K_J
3,8 BG2_NAND_WP#
R6028 47K_J
3 BG2_NAND_RE#
R6029 47K_J
3 BG2_NAND_WE#
R6030 47K_J
3 BG2_NAND_CLE
R6031 47K_J
3 BG2_NAND_ALE
VD_3P30
R6039
NC_47K_J
R6032 47K_J
4 STRP_NANDV18EN
VD_3P30
R6040
NC_47K_J
R6033 47K_J
4,15 STRP_NANDV25EN
VD_3P30_STB
R6015 4.7K_J R6021
R6016 NC_4.7K_J R6022
2 BG2_SM_STRP0
2 BG2_SM_STRP1
VD_3P30_STB
R6017 NC_4.7K_J R6023
R6018 NC_4.7K_J R6024
2 BG2_SM_STRP2
2 BG2_SM_STRP3
VD_3P30_STB
R6019 NC_4.7K_J
boot_src[0]
R6020 4.7K_J
boot_src[1]
4 STRP_BSRC0
4,12 BG2_SPDIFO
R6013 0_J
3 SPI_FLASH_BSRC0
R6014 0_J
3 SPI_FLASH_BSRC1
7 | 8 | 9 |
software_strap[4]
software_strap[3]
software_strap[2]
3,8 BG2_NAND_WP#
3 BG2_NAND_RE#
software_strap[1]
3 BG2_NAND_WE#
3 BG2_NAND_CLE
software_strap[0]
3 BG2_NAND_ALE
nandV18Enable
0: NAND uses 3.3V
1: NAND uses 1.8V
Default:0
nandV25Enable
0: NAND uses 3.3V
1: NAND uses 2.5V
Default:0
SM_STRP[1:0]: Boot up selection
NC_4.7K_J
00: Typical boot up 0 w/o power stable signal input
01: Typical boot up 1w/ power stable signal input
4.7K_J
(through GPIO[5] input)
10: New boot up as discussed in the SM MAS
11: Disable SM. Berlin SoC still can access the SM peripherals
Default: 00
4.7K_J
SM_STRP[3:2] Reserved
Default: 00
4.7K_J
R6025 47K_J
boot_src[1:0]
See table bellow
R6026 NC_47K_J
BootSrc[1:0] ADDR TYPE
2¡¦b00 FF80-0000¡¦ SPI-Secure boot
2¡¦b01 h NAND Flash boot
2¡¦b10 FF80-0000¡¦ eMMC
2¡¦b11 h SPI-Clear boot
FFFF-0C00¡¦
h
F000-0000¡¦
h
SECTION 4 - DIAGRAMS
10 | 11 | 12 |
VD_3P30
R6034 NC_4.7K_J
R6035 NC_4.7K_J
R6036 NC_4.7K_J
R6037 NC_4.7K_J
R6038 NC_4.7K_J
Jumpers need to be used to configure
software_strap[4:0], which will indicate
the system configurations, such as
memory size, More details, please
refer to user manual .
40