Status Register; Srq Mask Register - JDS Uniphase TB9 Series User Manual

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SRQ mask register

Status Register

The status register records errors and other events that have occurred in the filter (Table 10).
When an event occurs, the filter status logic sets the corresponding bit to 1. The status register
can be read at any time because the bits stay set until the register is read at least once.
Table 10: Status Register
Bit 7 Bit 6
self-test service
error request
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Bit 7 (self-test error) is set if a calibration error is detected after power-up or after the
self-test query (TST?) is executed. At all other times it is 0.
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Bit 6 (service request) is set when the interrupt request logic of the filter detects a reason to
generate a service request interrupt on the GPIB interface.
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Bit 5 (syntax error) is set when the parser detects a syntax error in a command mnemonic.
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Bit 4 (message available) is set when a message is available in the output buffer.
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Bit 2 (settled) is set when bit 2 in the condition register changes from 0 to 1.
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Bit 0 (parameter error) is set when a parameter value is out of the range of the TB9 filter.
The status register can be read with the status register query (STB?) or by serial polling the
GPIB interface. During power-up, the status register contains 0 and can only be read by serial
polling. After initial power-up, only the settled bit (bit 2) is set to 1. The clear status byte
command (CSB) and the clear device command (CLR) clear the status register. STB? also
clears the status register, but only if the service request bit (bit 6) is set to 1.
SRQ Mask Register
The SRQ mask register unmasks specific events in the status register that generate a service
request interrupt on the GPIB interface (Table 11). The SRQ mask command (SRE) writes to
the SRQ mask register. When a bit in the SRQ mask register is set to 1, the interrupt logic of
the filter monitors the corresponding event bit in the status register. When a bit changes from 0
to 1, a service request interrupt is generated and bit 6 in the status register is set.
Table 11: SRQ Mask Register
Bit 7 Bit 6
self-test n/a
error
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Status Register
Bit 5 Bit 4
syntax message
error available
SRQ Mask Register
Bit 5 Bit 4
syntax message
error available
Bit 3 Bit 2
0 settled
Bit 3 Bit 2
n/a settled
Operating and Maintenance Instructions – 25
Bit 1 Bit 0
0 parameter
error
Bit 1 Bit 0
n/a parameter
error