Sony XVS-8000-C Service Manual page 55

• Control of Network PHY
CADEC
FPGA configuration
FPGA configuration data is stored in the flash memory (IC207, IC2807). After power is turned on, the CADEC (IC201,
IC2801) reads necessary data from the flash memory and performs FPGA configuration.
Nios boot
After the configuration has been completed, the CADEC releases FPGA reset to boot the Nios.
Writing installation data
Installation data used in the production process is stored in the flash memory (IC207, IC208, IC2807, IC2808) through
the local bus connected to the CA-92 board.
Update
Version update of the NET-28 board on the market is enabled on the web using the Ethernet port of the Net Media
interface. Package data including the following data is released, allowing batch update of all data.
• NeptuneII firmware
• Nios2 firmware
• FPGA configuration
XVS-8000-C/XVS-8000
6-9