DG TOE10G-IP Setup Manual

Fpga setup with cpu demo

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dg_toeudp10gip_fpgasetup_intel.doc

FPGA setup TOE/UDP10G-IP with CPU Demo

Rev3.0 26-Aug-20

This document describes how to setup FPGA board and prepare the test environment for running

TOE10G-IP or UDP10G-IP demo. The user can setup two test environments for transferring TCP

data or UDP data via 10Gb Ethernet connection by using TOE10G-IP or UDP10G-IP, as shown in

Figure 1-1.

Figure 1-1 Two test environments for running the demo

First uses one FPGA board and Test PC with 10Gb Ethernet card for transferring the data. TestPC

runs test application, i.e. tcpdatatest (half-duplex test for TOE10G-IP), tcp_client_txrx_40G

(full-duplex test for TOE10G-IP) or udpdatatest (test application for UDP10G-IP). Also, NiosII

terminal is run on Test PC to be user interface console.

Second uses two FPGA boards which may be different board. Both boards run TOE10G-IP or

UDP10G-IP demo with assigning the different initialization mode (Client or Server) for transferring

data.

26-Aug-20

Page 1

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Summary of Contents for DG TOE10G-IP

Page 1 This document describes how to setup FPGA board and prepare the test environment for running TOE10G-IP or UDP10G-IP demo. The user can setup two test environments for transferring TCP data or UDP data via 10Gb Ethernet connection by using TOE10G-IP or UDP10G-IP, as shown in Figure 1-1.
Page 2 For Stratix10 GX board only, QSFP+ to four SFP+ cable • micro USB cable for JTAG connection • Test application provided by Design Gateway for running on Test PC: TOE10G-IP: “tcpdatatest.exe” and “tcp_client_txrx_40G.exe” UDP10G-IP: “udpdatatest.exe” • QuartusII Programmer and NiosII command shell, installed on PC Note: Example hardware for running the demo is listed as follows.
Page 3 Note: Four LEDs are applied to show IP timeout status when the configuration file of the demo uses 1-hour timeout TOE10G-IP/UDP10G-IP. After running for 1 hour, the IP stops the operation. All LEDs are blinked to notify that the IP now is timeout. User needs to reconfigure FPGA to restart the test.
Page 4 Figure 1-2 TOE10G-IP/UDP10G-IP with CPU demo (FPGA<->PC) on Arria10 GX 26-Aug-20 Page 4...
Page 5 Figure 1-3 TOE10G-IP/UDP10G-IP with CPU demo (FPGA<->PC) on Cyclone10 GX 26-Aug-20 Page 5...
Page 6 Figure 1-4 TOE10G-IP/UDP10G-IP with CPU demo (FPGA<->PC) on Stratix10 GX 26-Aug-20 Page 6...
Page 7 dg_toeudp10gip_fpgasetup_intel.doc The step to setup test environment by using FPGA and PC is described in more details as follows. 1) Turn off power switch and connect power supply to FPGA board. 2) Connect micro USB cable from FPGA board to PC for JTAG programming and JTAG UART.
Page 8 dg_toeudp10gip_fpgasetup_intel.doc 4) Turn on power switch on FPGA board. 5) For Arria10 SoC board, set programmable clock to 322.265625 MHz by using “Clock Control” application as following step. a. Open “Clock Controller” application. b. Select Si5338 tab (U50) and set CLK3 frequency = 322.265625 MHz. c.
Page 9 dg_toeudp10gip_fpgasetup_intel.doc 6) Open QuartusII Programmer to program FPGA through USB-1 by following step. a. Click “Hardware Setup…” to select USB-BlasterII[USB-1]. b. Click “Auto Detect” and select FPGA number. c. Select Arria 10/Cyclone 10/Stratix 10 device icon. d. Click “Change File” button, select SOF file in pop-up window and click “open” button. e.
Page 10 Type “nios2-terminal” to run the console. Figure 1-9 Run NiosII terminal b. Input ‘0’ to initialize TOE10G-IP/UDP10G-IP in client mode (asking PC MAC address by sending ARP request). c. Default parameter in client mode is displayed on the console.
Page 11 dg_toeudp10gip_fpgasetup_intel.doc d. User enters ‘x’ to skip parameter setting for using default parameters to begin system initialization, as shown in Figure 1-12. If user enters other keys, the menu for changing parameter is displayed, similar to “Reset TCPIP parameters” menu. The example when running the main menu is described in “dg_toe10gip_cpu_instruction”...
Page 12 For Stratix10 GX board, QSFP+ to four SFP+ cable • Two micro USB cables, one cable for connecting one FPGA board to PC • QuartusII Programmer for programming FPGA and NiosII command shell, installed on PC Figure 2-1 TOE10G-IP/UDP10G-IP with CPU demo (FPGA<->FPGA) 26-Aug-20 Page 12...
Page 13 dg_toeudp10gip_fpgasetup_intel.doc The step to setup test environment by using two FPGAs is described in more details as follows. Follow step 1) – 5) of topic 1 (Test environment setup when using FPGA and PC) to prepare FPGA board. Warning: For Arria10 SoC board, Clock controller for programming clock to 322.265625 MHz could be used when only one FPGA is connected to PC.
Page 14 dg_toeudp10gip_fpgasetup_intel.doc 2) Connect micro USB cable of each FPGA board to PC. After that, PC detects two USB-Blaster cables as USB-1 and USB-2 from two USB connections with two FPGA boards. Follow step 6) of topic 1 (Test environment setup when using FPGA and PC) for FPGA configuration.
Page 15 dg_toeudp10gip_fpgasetup_intel.doc 4) Open NiosII Command Shell. a. Run nios2-terminal --cable 1 command for FPGA#1 b. Run nios2-terminal –cable 2 command for FPGA#2 Figure 2-5 Run NiosII terminal on two consoles 5) Set the input to the console. a. Set ‘1’ on Serial console of FPGA board#1 for running server mode. b.
Page 16 6) Input ‘x’ to use default parameters or other keys to change parameters. The parameters of server mode must be set before client mode. When running TOE10G-IP, a. Set parameters on server Serial console. b. Set parameters on client Serial console to start IP initialization by transferring ARP packet.
Page 17 dg_toeudp10gip_fpgasetup_intel.doc When running UDP10G-IP, a. For server mode, if user does not change default parameters, input ‘x’ to skip parameter setting. b. For client mode, user must change target port number (Target->FPGA) to use same value as target port number (FPGA->Target). c.
Page 18: Revision History
Correct optical cable in Figures and the descriptions 5-Feb-19 Add Arria 10 GX board and change software to tcp_client_txrx_40G 31-May-19 Add timeout LED descriptions 20-Aug-19 Add Cyclone10 GX board 18-Jun-20 Remove test result on the console 26-Aug-20 TOE10G-IP and UDP10G-IP 26-Aug-20 Page 18...

This manual is also suitable for:

Udp10g-ip