DG TOE10G IP Demo Instructions
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DG TOE10G IP Demo Instructions

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TOE10G IP with CPU Demo Instruction
Contents
1
Overview ............................................................................................................................... 2
Part A TOE10G IP with CPU demo by using FPGA and PC ........................................................ 3
2
Environment Setup ................................................................................................................ 3
3
PC Setup ............................................................................................................................... 8
3.1
IP Setting ........................................................................................................................ 8
3.2
Speed and Frame Setting ............................................................................................... 9
3.3
Power Option Setting .................................................................................................... 12
4
FPGA board setup ............................................................................................................... 13
5
Main menu .......................................................................................................................... 19
5.1
Show TCPIP parameters .............................................................................................. 19
5.2
Reset TCPIP parameters .............................................................................................. 20
5.3
Send Data Test ............................................................................................................. 22
5.4
Receive Data Test ......................................................................................................... 25
5.5
Full duplex Test ............................................................................................................. 28
Part B TOE10G IP with CPU demo by using two FPGAs .......................................................... 30
6
Environment Setup .............................................................................................................. 30
7
FPGA board setup ............................................................................................................... 32
8
Main menu .......................................................................................................................... 34
8.1
Display current parameter............................................................................................. 34
8.2
Reset TCPIP parameters .............................................................................................. 35
8.3
Send Data Test (server to client) ................................................................................... 37
8.4
Receive Data Test (client to server) .............................................................................. 39
8.5
Full duplex Test ............................................................................................................. 41
9
Revision History .................................................................................................................. 43
23-Aug-19
Rev1.3 23-Aug-19
Page 1

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  • Page 1: Table Of Contents

    TOE10G IP with CPU Demo Instruction Rev1.3 23-Aug-19 Contents Overview ..........................2 Part A TOE10G IP with CPU demo by using FPGA and PC ............3 Environment Setup ........................ 3 PC Setup ..........................8 IP Setting ........................8 Speed and Frame Setting ....................9 Power Option Setting ....................

  • Page 2: Overview

    1 Overview The demo is designed to run TOE10G IP for transferring 10 Gb Ethernet data by using TCP/IP protocol. Two test environments can be setup for the demo, as shown in Figure 1-1. First one (Test Env#A) uses one FPGA board transferring data with Test PC. More details to run the demo by using FPGA and Test PC are described in PartA.

  • Page 3: Part A Toe10G Ip With Cpu Demo By Using Fpga And Pc

    Part A TOE10G IP with CPU demo by using FPGA and PC To transfer data between TOE10G IP and Test PC, user selects to run half-duplex or full-duplex demo. “tcpdatatest” application is run on Test PC for half-duplex demo (sending data from TOE10G IP to PC or receiving data from PC to TOE10G IP).
  • Page 4 Figure 2-1 TOE10G IP with CPU demo (FPGA <-> PC) on ZC706 23-Aug-19 Page 4...
  • Page 5 Figure 2-2 TOE10G IP with CPU demo (FPGA <-> PC) on ZCU102 23-Aug-19 Page 5...
  • Page 6 Figure 2-3 TOE10G IP with CPU demo (FPGA <-> PC) on KCU105 23-Aug-19 Page 6...
  • Page 7 Figure 2-4 TOE10G IP with CPU demo (FPGA <-> PC) on VCU118 23-Aug-19 Page 7...

  • Page 8: Pc Setup

    dg_toe10gip_cpu_instruction_xilinx_en.doc 3 PC Setup Before running demo, please check the network setting on PC. Following shows the example of the network setting. 3.1 IP Setting Figure 3-1 Setting IP address for PC 1) Open Local Area Connection Properties of 10-Gb connection, as shown in the left window of Figure 3-1.

  • Page 9: Speed And Frame Setting

    dg_toe10gip_cpu_instruction_xilinx_en.doc 3.2 Speed and Frame Setting Figure 3-2 Set frame size = jumbo frame 1) On Local Area Connection Properties window, click “Configure” as shown in Figure 3-2. 2) On Advanced Tab, select “Jumbo Packet”. Set Value to “9014 Bytes” for Jumbo Frame support or set value to “Disabled”...
  • Page 10 dg_toe10gip_cpu_instruction_xilinx_en.doc 3) On Link Speed, select “10 Gbps Full Duplex” for running 10-Gigabit speed, as shown in Figure 3-3. Figure 3-3 Set link speed = 10 Gbps 23-Aug-19 Page 10...
  • Page 11 dg_toe10gip_cpu_instruction_xilinx_en.doc 4) On Advanced Tab, select “Performance Options” and click “Properties” button. 5) On “Performance Options” window, select “Low Latency Interrupts” and click “Properties” button. 6) On “Low Latency Interrupts” window, select “Use Low Latency Interrupts” and click “OK” button. 7) Click “OK”...

  • Page 12: Power Option Setting

    dg_toe10gip_cpu_instruction_xilinx_en.doc 3.3 Power Option Setting 1) Open Control Panel and select Power Options as shown in the left window of Figure 3-5. 2) Change setting to High Performance as shown in the right window of Figure 3-5. Figure 3-5 Power options 23-Aug-19 Page 12...

  • Page 13: Fpga Board Setup

    dg_toe10gip_cpu_instruction_xilinx_en.doc 4 FPGA board setup 1) Check DIPSW and jumper setting on FPGA board. a) Board setting on ZC706 board is shown in Figure 4-1. Insert jumper to J17 to enable Tx SFP+ Set SW11 to configure PS from JTAG Set SW4 to use USB-JTAG.
  • Page 14 dg_toe10gip_cpu_instruction_xilinx_en.doc c) Board setting on KCU105 board is shown in Figure 4-3. Insert jumper to J6 to enable Tx SFP+. Figure 4-3 Insert jumper to enable SFP+ on KCU105 2) Connect micro USB cable from FPGA board to PC for JTAG programming. 3) Connect micro USB cable (ZCU102/KCU105/VCU118 board) or mini USB cable (ZC706 board) from FPGA board to PC for USB UART.
  • Page 15 dg_toe10gip_cpu_instruction_xilinx_en.doc b) For VCU118, insert QSFP+ to 4 SFP+ cable between FPGA board and PC. Use SFP+ no.1 to connect to FPGA as shown in Figure 4-5 Figure 4-5 QSFP+ channel using on VCU118 board 6) Power on FPGA board. 7) Open Serial console.
  • Page 16 dg_toe10gip_cpu_instruction_xilinx_en.doc 8) Download configuration file and firmware to FPGA board a) For ZCU102/ZC706 board, open Vivado TCL shell and change current directory to download folder which includes demo configuration file. Type “toe10cputest_zcu102 (or zc706).bat, as shown in Figure 4-7. Figure 4-7 Example command script for download to ZC706/ZCU102 by Vivado tool b) For KCU105 board, use Vivado tool to program configuration file, as shown in Figure Figure 4-8 Program FPGA by Vivado 23-Aug-19...
  • Page 17 9) Input ‘0’ to initialize TOE10G IP in client mode (ask PC MAC address by sending ARP request). 10) Default parameter in client mode is displayed on the console. Figure 4-9 Message after system boot-up If Ethernet connection has the problem and the status is linked down, the error message will be displayed on the console instead of welcome message, as shown in Figure 4-10.
  • Page 18 dg_toe10gip_cpu_instruction_xilinx_en.doc 11) User inputs ‘x’ to skip parameter setting for using default parameters to initialize system, as shown in Figure 4-11. If user inputs other keys, the menu to change parameter will be displayed. The example to change parameter is shown in topic 5.2 (Reset TCPIP parameters).

  • Page 19: Main Menu

    0x00 – 0x3F (0-63). The unit size of threshold value is 1 Kbyte. Default value is 0 (disable window update feature). 2) Mode: Set mode to TOE10G IP to act as server or client. To run with PC, please input ‘0’ to initialize the IP in client mode.

  • Page 20: Reset Tcpip Parameters

    There are seven parameters to set in this menu. Each parameter is verified by CPU. The parameter is updated to TOE10G IP when the input is valid. If the input is not valid, the parameter will not change. After user inputs all parameters, IP is reset. The description of each parameter is shown in topic 5.1(Show TCPIP parameters) and the range of each...
  • Page 21 dg_toe10gip_cpu_instruction_xilinx_en.doc Figure 5-2 Change IP parameter result 23-Aug-19 Page 21...

  • Page 22: Send Data Test

    “0x” to be a prefix when the input is hexadecimal unit. Note: If packet size is more than 1456, the packet output from TOE10G IP will be jumbo frame. In this case, Test PC must support jumbo frame.
  • Page 23 dg_toe10gip_cpu_instruction_xilinx_en.doc Figure 5-3 Send data test by using non-jumbo frame Figure 5-4 Send data test by using jumbo frame 23-Aug-19 Page 23...
  • Page 24 dg_toe10gip_cpu_instruction_xilinx_en.doc If the input is invalid, “Out-of-range input” or “Invalid input” will be displayed. After that, the operation is cancelled, as shown in Figure 5-5 - Figure 5-7. Figure 5-5 Error from invalid transfer size Figure 5-6 Error from invalid packet size Figure 5-7 Error from invalid mode 23-Aug-19 Page 24...

  • Page 25: Receive Data Test

    dg_toe10gip_cpu_instruction_xilinx_en.doc 5.4 Receive Data Test To transfer data from PC to FPGA, select ‘3’ to run receive data test on FPGA and run “tcpdatatest.exe” on PC to send data. User inputs test parameters on FPGA for receiving data through Serial console. On PC, user inputs test parameters of “tcpdatatest” to send data through Command prompt.
  • Page 26 dg_toe10gip_cpu_instruction_xilinx_en.doc Figure 5-8 Receive data test without data verification Figure 5-9 Receive data test when enable data verification 23-Aug-19 Page 26...
  • Page 27 dg_toe10gip_cpu_instruction_xilinx_en.doc Figure 5-10 Receive data test when data verification is failed 23-Aug-19 Page 27...

  • Page 28: Full Duplex Test

    dg_toe10gip_cpu_instruction_xilinx_en.doc 5.5 Full duplex Test Select ‘4’ to run full duplex test to transfer data between FPGA and PC in both directions at the same time. User inputs test parameters on FPGA through Serial console and inputs test parameters on PC through Command prompt. ”tcp_client_txrx_40G” application is called on PC to send and receive data by using same port number.
  • Page 29 dg_toe10gip_cpu_instruction_xilinx_en.doc Figure 5-11 Full duplex test without data verification Figure 5-12 Full duplex test with data verification 23-Aug-19 Page 29...

  • Page 30: Part B Toe10G Ip With Cpu Demo By Using Two Fpgas

    Part B TOE10G IP with CPU demo by using two FPGAs 6 Environment Setup Figure 6-1 shows the test environment of TOE10G IP with CPU demo by using two FPGAs. Please prepare following test environment. 1) Two FPGA development boards (ZC706/ZCU102/KCU105/VCU118) Note: Two FPGA boards may be same or different board.
  • Page 31 Figure 6-1 TOE10G IP with CPU demo (FPGA<->FPGA) by ZC706 and ZCU102 23-Aug-19 Page 31...

  • Page 32: Fpga Board Setup

    dg_toe10gip_cpu_instruction_xilinx_en.doc 7 FPGA board setup Please follow topic 4 (FPGA board setup) to prepare FPGA board and SFP+ connection for running the demo. After two FPGA boards have been configured completely, Serial console displays the menu to select client mode or server mode. The step after FPGA configuration is described as follows.
  • Page 33 dg_toe10gip_cpu_instruction_xilinx_en.doc 2) Input ‘x’ to use default parameters or other keys to change parameters. Please complete to set parameters on server Serial console before client Serial console. Server must be reset to wait ARP packet sent by client when running initialization. After finishing parameter setting and reset process, IP starts initialization process.

  • Page 34: Main Menu

    0x00 – 0x3F (0-63). The unit size of threshold value is 1 Kbyte. Default value is 0 (disable window update feature). 2) Mode: Set mode to TOE10G IP to act as server or client. Input ‘0’ for client and ‘1’ for server.

  • Page 35: Reset Tcpip Parameters

    There are seven parameters to set in this menu. Each parameter is verified by CPU. The parameter is updated to TOE10G IP when the input is valid. If which input is not valid, the parameter will not change. After user inputs all parameters, IP is reset. The description of each parameter is shown in topic 8.1(Display current parameter) and the range of each...
  • Page 36 dg_toe10gip_cpu_instruction_xilinx_en.doc Figure 8-2 Change IP parameter result 23-Aug-19 Page 36...

  • Page 37: Send Data Test (Server To Client)

    dg_toe10gip_cpu_instruction_xilinx_en.doc 8.3 Send Data Test (server to client) To transfer data from server to client, select ‘2’ to run send data test on server FPGA and select ‘3’ to run receive data test on client FPGA. User inputs test parameters through Serial console.
  • Page 38 dg_toe10gip_cpu_instruction_xilinx_en.doc Figure 8-3 Send data test by using non-jumbo frame Figure 8-4 Send data test by using jumbo frame 23-Aug-19 Page 38...

  • Page 39: Receive Data Test (Client To Server)

    dg_toe10gip_cpu_instruction_xilinx_en.doc 8.4 Receive Data Test (client to server) To transfer data from client to server, select ‘3’ to run receive data test on the server FPGA and select ‘2’ to run send data test on the client FPGA. User inputs test parameters through Serial console.
  • Page 40 dg_toe10gip_cpu_instruction_xilinx_en.doc Figure 8-5 Receive data test with data verification 23-Aug-19 Page 40...

  • Page 41: Full Duplex Test

    dg_toe10gip_cpu_instruction_xilinx_en.doc 8.5 Full duplex Test Select ‘4’ to run full duplex test on server FPGA and client FPGA to transfer data in both directions at the same time. User inputs test parameters through Serial console. The sequence to run the test is shown as below. 1) On Serial console of server, input four parameters in full duplex test.
  • Page 42 dg_toe10gip_cpu_instruction_xilinx_en.doc Figure 8-6 shows full duplex test. The left window is Serial console from FPGA running as server and the right window is Serial console from FPGA running as client. Figure 8-6 Full duplex test with data verification 23-Aug-19 Page 42...

  • Page 43: Revision History

    dg_toe10gip_cpu_instruction_xilinx_en.doc 9 Revision History Revision Date Description 17-Jan-18 Initial version release 4-Apr-18 Add Part B (FPGA <-> FPGA test) 26-Feb-19 Add KCU105 board and change software to tcp_client_txrx_40G 23-Aug-19 Add VCU118 board 23-Aug-19 Page 43...

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