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DG NVMeG4-IP Instructions Manual

Nvme ip with pcie gen4 soft ip
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dg_nvmeg4ip_instruction_xilinx_en.doc
NVMe IP with PCIe Gen4 Soft IP demo instruction
This document describes the instruction to run NVMeG4-IP demo on FPGA development board
by using the PCIe adapter board, AB18-PCIeX16 board. The demo is designed to write and verify
data with NVMe Gen4 SSD. User controls the test operation through Serial console.
1 Environment Requirement
To run the demo on FPGA development board, please prepare following environment.
1) Supported FPGA Development board: VCU118
2) PC installing Xilinx programmer software (Vivado) and Serial console software such as
TeraTerm
3) AB18-PCIeX16 board, provided by Design Gateway.
https://dgway.com/ABseries_E.html
4) ATX power supply for AB18.
5) Xilinx power adapter for FPGA board
6) PCIe Gen4 NVMe SSD
7) Two micro USB cables for programming FPGA and Serial console, connecting between
FPGA board and PC
20-Apr-20
Rev1.1
20-Apr-20
Page 1

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Summary of Contents for DG NVMeG4-IP

  • Page 1 Rev1.1 20-Apr-20 This document describes the instruction to run NVMeG4-IP demo on FPGA development board by using the PCIe adapter board, AB18-PCIeX16 board. The demo is designed to write and verify data with NVMe Gen4 SSD. User controls the test operation through Serial console.
  • Page 2 Figure 1-1 NVMeG4-IP demo environment setup on VCU118 20-Apr-20 Page 2...

  • Page 3: Demo Setup

    dg_nvmeg4ip_instruction_xilinx_en.doc 2 Demo setup 1) Power off system. Then, connect ATX power supply to AB18-PCIeX16 board and Xilinx power adapter to FPGA development board. Figure 2-1 Power connection 2) Confirm that, • Two mini jumpers are inserted at J5 connector on AB18. •...
  • Page 4 dg_nvmeg4ip_instruction_xilinx_en.doc 3) Connect two micro USB cables between FPGA board and PC for FPGA programming and Serial console. Figure 2-3 USB cable connection 4) Power on FPGA development board and AB18 adapter board. Figure 2-4 Turn on power switch 5) On PC, the additional COM ports are detected after connecting USB cables to FPGA board.
  • Page 5 dg_nvmeg4ip_instruction_xilinx_en.doc 6) Download configuration file and firmware to FPGA board by using Vivado, as shown in Figure 2-6. Figure 2-6 Programmed by Vivado 20-Apr-20 Page 5...
  • Page 6 dg_nvmeg4ip_instruction_xilinx_en.doc 7) Check LED status on FPGA board. The description of LED is as follows. Table 2-1 LED Definition GPIO LED Normal operation Clock is not locked or reset button is pressed System is busy Idle status IP Error detect Normal operation Data verification fail Normal operation 8) After completely FPGA programming, LED[0] and LED[1] turn on until finishing the...
  • Page 7 dg_nvmeg4ip_instruction_xilinx_en.doc 3 Test Menu 3.1 Identify Command Select ‘0’ to send Identify command to NVMe SSD. Figure 3-1 Test result when running Identify command After finishing the operation, the SSD information output from Identify command is displayed. The console shows three values. 1) SSD model number: This value is decoded from Identify controller data.
  • Page 8 dg_nvmeg4ip_instruction_xilinx_en.doc 3.2 Write Command Select ‘1’ to send Write command to NVMe SSD. Normal Green: User input Blue: Output to user Input test parameter Current transfer size Output performance Figure 3-2 Input and test result when running Write command User inputs three parameters as follows. 1) Start Address: Input start address to write SSD as 512-byte unit.
  • Page 9 dg_nvmeg4ip_instruction_xilinx_en.doc Figure 3-3 Example Test data of the 1 and 2 512 byte by using increment/LFSR pattern Test data in SSD is split into 512-byte unit. For incremental, decremental, or LFSR pettern, each 512-byte data has unique 64-bit header which consists of 48-bit address (in 512-byte unit) and 16-bit zero value.
  • Page 10 dg_nvmeg4ip_instruction_xilinx_en.doc When user runs Write or Read command with 4-Kbyte LBA SSD, there is the message displaying on the console to show the input limitation which must be aligned to 8 as shown in Figure 3-4. When the input does not align to 8, “Invalid input” is displayed and the operation is cancelled.
  • Page 11 “Invalid input” is displayed when some inputs are invalid or unaligned to 8 (when connecting to 4-KB LBA SSD). Note: The read performance result is measured by customized NVMeG4-IP core with extended buffer size to achieve the best read performance of the SSD.
  • Page 12 dg_nvmeg4ip_instruction_xilinx_en.doc Figure 3-7 shows error message when data verification is failed. “Verify fail” is displayed with the information of the 1 failure data, i.e. the error byte address, the expected value, and the read value. User can enter any keys to cancel the read operation or wait until finishing Read command. Similar to the normal condition, the output performance is displayed on the console when the user does not enter any keys to stop the operation.
  • Page 13 dg_nvmeg4ip_instruction_xilinx_en.doc SMART Command Select ‘3’ to send SMART command to NVMe SSD. Figure 3-8 Test result when running SMART command After finishing the operation, SMART/Health Information (output from SMART command) is be displayed as shown in Figure 3-8. The console shows six parameters, described as follows.
  • Page 14 dg_nvmeg4ip_instruction_xilinx_en.doc 3.5 Flush Command Select ‘4’ to send Flush command to NVMe SSD. Figure 3-9 Test result when running Flush command “Flush Command Complete” is displayed after finishing Flush operation. 20-Apr-20 Page 14...
  • Page 15 dg_nvmeg4ip_instruction_xilinx_en.doc 3.6 Shutdown Command Select ‘5’ to send Shutdown command to NVMe SSD. Figure 3-10 Shutdown Command with confirmation The confirmation message is displayed on the console. User enters ‘y’ or ‘Y’ to continue the operation or enters other keys to cancel the operation. After finishing Shutdown operation, “Shutdown command is complete”...

  • Page 16: Revision History

    dg_nvmeg4ip_instruction_xilinx_en.doc 4 Revision History Revision Date Description 29-Jan-20 Initial version release 20-Apr-20 Remove power adapter cable from AB18 20-Apr-20 Page 16...