Expansion Header Signal Mapping - Texas Instruments XDS110 User Manual

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Alternate Functions
GPIO (PB5), ADC
(AIN11), I2C5 Data
GPIO (PB4), ADC
(AIN10), I2C5 Clock
GPIO (PE4), ADC (AIN9)
GPIO (PE5), ADC (AIN8)
Ground
ADC (AIN1), GPIO (PE2)
ADC (AIN2), GPIO (PE1)
GPIO (PB0), CAN1 RX,
UART1 RX, I2C5 Clock
GPIO (PC4), UART7 RX
GPIO (PB1), CAN1 TX,
UART1 TX, I2C5 Data
Ground
Digital 3.3 V
Digital 3.3 V
SPRUI94 – January 2017
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Table 2. Expansion Header Signal Mapping
Tiva XDS110 Signal
Pin
Pin Name
120 ET_SSICLK 1
121 ET_SSIFSS 3
123 ET_SSIDAT0 5
124 ET_SSIDAT1 7
GND 9
13 ET_AIN1 11
14 ET_AIN2 13
95 ET_PB0 15
25 ET_PC4 17
96 ET_PB1 19
POD_NON_ET
21
_VCC_SUPPLY
DEBUG_TARGET
23
_VDD_IN
GND 25
E3V3 27
E3V3 29
Copyright © 2017, Texas Instruments Incorporated
XDS110 Signal
Pin Tiva Pin
Name
2 ET_PN0 107
4 ET_PN1 108
6 ET_PN2 109
8 ET_PN3 110
10 GND
12 ET_SCL 112
14 ET_SDA 111
16 ET_PM2 76
18 ET_PH3 32
20 ET_PC5 27
POD_NON_ET
22
_VCC_SUPPLY
DEBUG_TARGET
24
_VDD_IN
26 GND
28 E5V0
30 E5V0
Probe Interfaces
Alternate Functions
GPIO (PN0)
GPIO (PN1)
GPIO (PN2)
GPIO (PN3)
Ground
GPIO (PN5)
GPIO (PN4)
GPIO (PM3),
Timer3 CCP0
GPIO (PH3)
GPIO (PC5), UART7 TX
Ground
Digital 5 V
Digital 5 V
11
XDS110 Debug Probe