Model Technology Modelsim; Verilog; Vhdl - Xilinx LogiCore LogiCore PCI v3.0 Getting Started Manual

R
NC-Verilog processes the simulation files and exits. The testbench prints status messages
to the console. After the simulation completes, view the ncverilog.log file to check for
errors.
The Simvision browser may be used to view the simulation results. Simvision is started
with the following command:

Model Technology ModelSim

Before attempting timing simulation, ensure that the ModelSim environment is properly
configured for use. In addition, you must have successfully completed the implementation
phase using the Xilinx tools.

Verilog

1.
2.
3.
4.
5.
This compiles all modules, loads them into the simulator, displays the waveform viewer,
and runs the simulation.

VHDL

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56
simvision
Move into the timing simulation directory and copy the back-annotated timing models
from the implementation directory:
cd <Install Path>/verilog/example/post_sim
cp ../xilinx/pcim_top_routed.v .
cp ../xilinx/pcim_top_routed.sdf .
Edit the ping_tb.f file. This file lists command line arguments, and is shown below:
../source/ping_tb.v
../source/stimulus.v
../source/busrecord.v
../source/dumb_arbiter.v
../source/dumb_targ32.v
../source/dumb_targ64.v
../source/glbl.v
./pcim_top_routed.v
+libext+.vmd+.v
-y <Xilinx Install Path>/verilog/src/simprims
Modify the library search path by changing <Xilinx Install Path> to match the
Xilinx installation directory. Save the file.
Invoke ModelSim, and make sure that the current directory is set to:
<Install Path>/verilog/example/post_sim
Type the following to run the simulation:
do modelsim.do
Navigate to the timing simulation directory and copy the back-annotated timing
models from the implementation directory:
cd <Install Path>/vhdl/example/post_sim
cp ../xilinx/pcim_top_routed.vhd .
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Chapter 7: Timing Simulation
PCI v3.0.151 Getting Started Guide
UG157 August 31, 2005