Xilinx LogiCore LogiCore PCI v3.0 Getting Started Manual
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Xilinx LogiCore LogiCore PCI v3.0 Getting Started Manual

Xilinx LogiCore LogiCore PCI v3.0 Getting Started Manual

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LogiCORE™
PCI v3.0

Getting Started Guide

UG157 August 31, 2005
v3.0.151
R

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Summary of Contents for Xilinx LogiCore LogiCore PCI v3.0

  • Page 1: Getting Started Guide

    LogiCORE™ PCI v3.0 Getting Started Guide UG157 August 31, 2005 v3.0.151...
  • Page 2 Specification. Xilinx reserves the right to make changes, at any time, to the Specification as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Specification.
  • Page 3 Version 06/24/02 Initial Xilinx release of corporate-wide common template set, used for User Guides, Tutorials, Release Notes, Manuals, and other lengthy, multiple-chapter documents created by both CMP and ITP. See related documents for further information. Descriptions for revisions prior to v3.0 have been abbreviated. For a full summary of revision changes prior to v3.0, refer to v2.2.1 template set.
  • Page 4 PCI v3.0.151 Getting Started Guide www.xilinx.com UG157 August 31, 2005...

  • Page 5: Table Of Contents

    ......... 40 www.xilinx.com PCI v3.0.151 Getting Started Guide...
  • Page 6 Exemplar LeonardoSpectrum Xilinx XST ............52...

  • Page 7: Preface: About This Guide

    Verilog-HDL and VHDL. Guide Contents This manual contains the following chapters: • Chapter 1, “Getting Started” additional resources, technical support, and submitting feedback to Xilinx. • Chapter 2, “Installing and Licensing the Core” and licensing the core. • Chapter 3, “Family Specific Considerations”...

  • Page 8: Additional Resources

    Additional Resources For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this website. You can also directly access these resources using the provided URLs. Resource Tutorials Answer Browser Application Notes Data Sheets...

  • Page 9: Online Document

    ... locn; Meaning or Use Cross-reference link to a for details. location in the current document for details. Go to Hyperlink to a website (URL) for the latest speed files. www.xilinx.com Example Example “Additional Resources” “Title Formats” in Chapter http://www.xilinx.com...
  • Page 10 Preface: About This Guide www.xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005...

  • Page 11: Chapter 1: Getting Started

    PCI User Guide Further information is available in the PCI Local Bus Specification, available from the PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 page: Mindshare PCI System Architecture PCI Special Interest Group www.xilinx.com Chapter 1 text, and the site.

  • Page 12: Technical Support

    For technical support, visit www.xilinx.com/support. Questions are routed to a team of engineers with expertise using the PCI interface. Xilinx provides technical support for use of this product as described in the PCI User Guide and the PCI Getting Started Guide. Xilinx cannot guarantee timing, functionality, or support of this product for designs that do not follow these guidelines.

  • Page 13: Chapter 2: Installing And Licensing The Core

    PCI lounge, you must purchase the core. PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Xilinx LogiCORE Site License Agreement Agreement, which conform to the terms of the PCI/PCI-X lounge frequently to make sure that you are www.xilinx.com...

  • Page 14: Core Generator Ip Updates Installer

    If prompted to enter a log-in name and password, enter your Xilinx log-in and password. • If you are new to Xilinx, click Create an Account and follow the instructions to create an account. (After creating an account, you will be redirected to the page to download the core.) Click Install All Packages from Queue to download the update.

  • Page 15: Direct Download Of Standalone Core

    For additional assistance installing the IP Update, contact the Xilinx Hotline. Direct Download of Standalone Core The PCI core can be downloaded from the Xilinx website and used outside of the CORE Generator by downloading a .zip file containing the core and other necessary supporting files.

  • Page 16: Licensing Options

    Full functionality in the programmed device with no time-outs Obtaining a Full License After purchase, a full license for the Xilinx PCI core can be downloaded from the core’s lounge. To create and download a license file for use with the CORE Generator, do the...

  • Page 17: Installing Your License File

    After selecting a license option, an email will be sent to you that includes instructions for installing your license file. In addition, information about advanced licensing options and technical support is provided. PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 www.xilinx.com...
  • Page 18 Chapter 2: Installing and Licensing the Core www.xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005...

  • Page 19: Chapter 3: Family Specific Considerations

    33 MHz pcim_lc_33_5_s 2s150fg456_64_33.ucf 5.0V no guide file 64-bit 33 MHz pcim_lc_33_3_s 2s150fg456_64_33.ucf 3.3V no guide file 64-bit 66 MHz pcim_lc_66_3_d 2s150fg456_64_66.ucf 3.3V 2s150fg456_64_66.ncd 64-bit 33 MHz pcim_lc_33_5_s 2s200fg456_64_33.ucf 5.0V no guide file 64-bit www.xilinx.com Chapter 3 Constraints File/ Guide File...
  • Page 20 64-bit 66 MHz pcim_lc_66_3_d v300bg432_64_66.ucf 3.3V v300bg432_64_66.ncd 64-bit 33 MHz pcim_lc_33_5_s v300bg432_64_33.ucf 5.0V no guide file 64-bit 33 MHz pcim_lc_33_3_s v300bg432_64_33.ucf 3.3V no guide file 64-bit www.xilinx.com PCI v3.0.151 Getting Started Guide Constraints File/ Guide File UG157 August 31, 2005...
  • Page 21 64-bit 66 MHz pcim_lc_66_3_s 2v1000fg456_64_66.ucf 3.3V 2v1000fg456_64_66.ncd 64-bit 33 MHz pcim_lc_33_3_s 2v1000fg456_64_33.ucf 3.3V no guide file 64-bit 66 MHz pcim_lc_66_3_s 2vp7ff672_64_66.ucf 3.3V 2vp7ff672_64_66.ncd 64-bit 33 MHz pcim_lc_33_3_s 2vp7ff672_64_33.ucf 3.3V no guide file 64-bit www.xilinx.com Constraints File/ Guide File...
  • Page 22 33 MHz pcim_lc_33_3_s 3s1000fg456_64_33.ucf 3.3V no guide file 64-bit 33 MHz pcim_lc_33_3_s 3s1200efg400_64_33.ucf 3.3V no guide file 64-bit 33 MHz pcim_lc_33_3_g 4vlx25ff668_64_33g.ucf 3.3V no guide file 64-bit www.xilinx.com PCI v3.0.151 Getting Started Guide Constraints File/ Guide File UG157 August 31, 2005...
  • Page 23 66 MHz pcim_lc_66_3_r 4vlx20ff672_64_66r.ucf 3.3V no guide file 64-bit 33 MHz pcim_lc_33_5_s 2s030pq208_32_33.ucf 5.0V no guide file 32-bit 33 MHz pcim_lc_33_3_s 2s030pq208_32_33.ucf 3.3V no guide file 32-bit 33 MHz pcim_lc_33_5_s 2s050pq208_32_33.ucf 5.0V no guide file 32-bit www.xilinx.com Constraints File/ Guide File...
  • Page 24 33 MHz pcim_lc_33_3_s 2s100epq208_32_33.ucf 3.3V no guide file 32-bit 33 MHz pcim_lc_33_3_s 2s150epq208_32_33.ucf 3.3V no guide file 32-bit 33 MHz pcim_lc_33_3_s 2s200epq208_32_33.ucf 3.3V no guide file 32-bit www.xilinx.com PCI v3.0.151 Getting Started Guide Constraints File/ Guide File UG157 August 31, 2005...
  • Page 25 33 MHz pcim_lc_33_3_s v1000efg680_32_33.ucf 3.3V no guide file 32-bit 33 MHz pcim_lc_33_3_s 2v1000fg456_32_33.ucf 3.3V no guide file 32-bit 33 MHz pcim_lc_33_3_s 2vp7ff672_32_33.ucf 3.3V no guide file 32-bit 33 MHz pcim_lc_33_3_s 3s1000fg456_32_33.ucf 3.3V no guide file 32-bit www.xilinx.com Constraints File/ Guide File...
  • Page 26 32-bit 33MHz pcim_lc_33_3_r 4vsx35ff668_32_33r.ucf 3.3V no guide file 32-bit 33MHz pcim_lc_33_3_r 4vfx20ff672_32_33r.ucf 3.3V no guide file 32-bit 66 MHz pcim_lc_66_3r 4vlx25ff668_32_33r.ucf 3.3V no guide file 32-bit www.xilinx.com PCI v3.0.151 Getting Started Guide Constraints File/ Guide File UG157 August 31, 2005...
  • Page 27 See the product release notes included with the core for a complete directory structure and file list. PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Wrapper File Type 66 MHz pcim_lc_66_3r 4vsx35ff668_32_33r.ucf 3.3V no guide file 32-bit 66 MHz pcim_lc_66_3r 4vfx20ff672_32_33r.ucf 3.3V no guide file 32-bit www.xilinx.com Constraints File/ Guide File...
  • Page 28 PCI interface. Each guide file is specific to a particular device and PCI interface, and must always be used when required. Guide files are located in the <Install Path>/hdl/src/guide directory. If a guide file is required, use the appropriate guide file from the guide directory when processing designs with the Xilinx implementation tools. Table 3-2 specifies how many guided components and guided connections are included in each guide file.

  • Page 29: Device Initialization

    FPGA, to sample REQ64#. this can be accomplished. REQ64# PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Guide File Components RESISTOR RST# Figure 3-1: Sample SLOT64 Generation www.xilinx.com Connections Figure 3-1 shows how SLOT64...

  • Page 30: Datapath Output Clock Enable

    Input delay buffers are used to provide guaranteed hold time on all bus inputs. Where possible, the PCI interface targeting Virtex devices uses input delay elements present in the Chapter 3: Family Specific Considerations www.xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005...
  • Page 31 In this case, it is the responsibility of the user to verify the following: PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Implementation Table 3-3 shows the required settings for CFG[248:245] in Table 3-3 and use the appropriate constraints file for the design. www.xilinx.com Delay Setting “0000” “0000” “0000” “0000” “0001” “0000”...

  • Page 32: Regional Clock Usage

    BUFR driving three clock regions. See the Virtex-4 Datasheet and User Guide for more information about regional clocks. Chapter 3: Family Specific Considerations “Bus Clock Usage” www.xilinx.com PCI v3.0.151 Getting Started Guide for additional information Figure 3-2 UG157 August 31, 2005...
  • Page 33 Note that this does not apply to Virtex-4 designs using global clocks. Table 3-4: Virtex-4 Device and Package 64-bit Interfaces Package PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Figure 3-2: Regional Clocking Illustration Device LX15 LX25 SF363 FX12 www.xilinx.com BUFR 64-bit Interfaces none none none...

  • Page 34: Bus Clock Usage

    SX25 SX35 LX40 LX60 LX80 FF1148 LX100 LX160 SX55 LX100 FF1513 LX160 LX200 FX20 FF672 FX40 FX60 FX40 FF1152 FX60 FX100 FX100 FF1517 FX140 FF1760 FX140 www.xilinx.com 64-bit Interfaces none none PCI v3.0.151 Getting Started Guide UG157 August 31, 2005...

  • Page 35: Electrical Compliance

    . This may be considered the 3.3 volt system supply. or V will not venture beyond the parameters stated in the PCI Local www.xilinx.com to be set at 3.3 volts, and does not to be set at 3.3 volts, and do not...
  • Page 36 3.05 3.10 3.15 3.20 3.25 3.30 System Supply (V) Figure 3-3: Relationship For 3.3V Input Buffer Compliance shows the small range of supply voltage values where V www.xilinx.com 3.35 3.40 3.45 3.50 3.55 3.60 or V are technically CCINT PCI v3.0.151 Getting Started Guide...

  • Page 37: Generating Bitstreams

    Generating Bitstreams Figure 3-4 driver supply. Xilinx recommends the use of the circuit shown in other approaches using other regulators are possible. SUPPLY Virtex-II, Virtex-II Pro, Virtex-4, Spartan-3, and Spartan-3E devices, as specified in the relevant device data sheets, exhibit a 10 pF pin capacitance. This is compliant with the PCI Local Bus Specification, with one exception.
  • Page 38 CLK output of the PCI interface, which is supplied to the user application. Timing constraints for the user application must be generated with this in mind. www.xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005...

  • Page 39: Functional Simulation

    ../../src/xpci/pcim_lc.v +libext+.vmd+.v -y <Xilinx Install Path>/verilog/src/unisims -y <Xilinx Install Path>/verilog/src/simprims Modify the library search path by changing <Xilinx Install Path> to match the Xilinx installation directory, and then save the file. PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 www.xilinx.com...

  • Page 40: Model Technology Modelsim

    ../source/glbl.v ../../src/xpci/pci_lc_i.v ../../src/xpci/pcim_lc.v +libext+.vmd+.v -y <Xilinx Install Path>/verilog/src/unisims -y <Xilinx Install Path>/verilog/src/simprims This list does not include any configuration file, user application, top level wrapper, or testbench. These additional files are required for a meaningful simulation. To run the NC-Verilog simulation, type the following: ncverilog -f ping_tb.f...

  • Page 41: Vhdl

    Model Technology ModelSim Modify the library search path by changing <Xilinx Install Path> to match the Xilinx installation directory and then save the file. Most of the files listed are related to the example design and its testbench. For other testbenches, the following subset must be used for proper simulation of the PCI interface: ../source/glbl.v...
  • Page 42 <Install Path>/vhdl/example/func_sim Create the simprim and unisim libraries. This step only needs to be done once, the first time you perform a simulation: vlib simprim vcom -93 -work simprim <Xilinx Install Path>/vhdl/src/simprims/simprim_Vpackage_mti.vhd vcom -93 -work simprim <Xilinx Install Path>/vhdl/src/simprims/simprim_Vcomponents_mti.vhd vcom -93 -work simprim <Xilinx Install Path>/vhdl/src/simprims/simprim_VITAL_mti.vhd...

  • Page 43: Chapter 5: Synthesizing A Design

    • Synplicity Synplify v7.3 • Exemplar LeonardoSpectrum v2003a • Xilinx XST Synplicity Synplify Before attempting to synthesize a design, ensure that the Synplicity Synplify environment is properly configured. Verilog Start Synplify and choose File > New, or click the new file icon on the toolbar. The New dialog box appears.
  • Page 44 To add source files to the new project, click Add. The first file (used by any design that instantiates Xilinx primitives) is located in: <Synplicity Install Path>/lib/xilinx Navigate to the virtex.v file; then click Add to move this source file into the Files To Add list.
  • Page 45 Navigate to the source directory, select the cfg_ping.v, pcim_top.v, and ping.v files, and then click Add. PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Figure 5-8: Files to Add (LogiCORE Files) Figure 5-9: Select Files to Add Dialog Box (User Application) www.xilinx.com...
  • Page 46 Implementation dialog box, as shown in Figure 5-10: Main Project Window with Source Files and click OK to set the name of the result file and return pcim_top.edf Figure www.xilinx.com Chapter 5: Synthesizing a Design Figure 5-10. 5-11. PCI v3.0.151 Getting Started Guide...
  • Page 47 Mapping, are displayed. When the process is complete, Done is displayed. Note that Synplify may issue a number of warnings (are expected) about instantiated I/O cells and attributes used for other synthesis tools. PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Figure 5-11: Options for Implementation: Device www.xilinx.com...

  • Page 48: Vhdl

    Click OK to exit the dialog box and return to the project window. To add source files to the new project, click Add. The first file (used by any design that instantiates Xilinx primitives) is located in: <Synplicity Install Path>/lib/xilinx...
  • Page 49 (pci_lc_i.vhd and pcim_lc.vhd), and click Add to move these files into the Files To Add list. (Ctrl-click to select multiple files.) PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Figure 5-14: Select Files to Add (Library) Figure 5-15: Select Files to Add (LogiCORE Files) www.xilinx.com...
  • Page 50 EDIF files will be located in the synthesis directory. Figure 5-16. Figure 5-16: Project Window with Source Files and click OK to set the name of the result file and return pcim_top.edf www.xilinx.com Chapter 5: Synthesizing a Design PCI v3.0.151 Getting Started Guide UG157 August 31, 2005...

  • Page 51: Exemplar Leonardospectrum

    Note that if you run LeonardoSpectrum with the graphical user interface, the quicksetup form cannot be used to synthesize the design. Instead, choose File > Run Script from the menu. PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 Figure 5-17. Figure 5-17: Options for Implementation www.xilinx.com...

  • Page 52: Xilinx Xst

    The end result of the synthesis step is an EDIF file that is fed into the Xilinx implementation tools during the implementation step. In practice, the provided script file must be modified to accommodate other designs. To provide insight into the synthesis script, the major steps are presented below: Various synthesis options are set through the use of environment variables.

  • Page 53: Chapter 6: Implementing A Design

    ISE Foundation Before implementing a design, ensure that the Xilinx environment is properly configured and the design has been successfully synthesized. Navigate to the implementation directory: cd <Install Path>/hdl/example/xilinx...
  • Page 54 Chapter 6: Implementing a Design Table 3-1, page 19. The number of unrouted signals varies www.xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005...

  • Page 55: Timing Simulation

    ../source/glbl.v ./pcim_top_routed.v +libext+.vmd+.v -y <Xilinx Install Path>/verilog/src/simprims Modify the library search path by changing <Xilinx Install Path> to match the Xilinx installation directory and save the file. To run the NC-Verilog simulation: ncverilog -f ping_tb.f PCI v3.0.151 Getting Started Guide UG157 August 31, 2005 www.xilinx.com...

  • Page 56: Model Technology Modelsim

    ../source/glbl.v ./pcim_top_routed.v +libext+.vmd+.v -y <Xilinx Install Path>/verilog/src/simprims Modify the library search path by changing <Xilinx Install Path> to match the Xilinx installation directory. Save the file. Invoke ModelSim, and make sure that the current directory is set to: <Install Path>/verilog/example/post_sim Type the following to run the simulation: do modelsim.do...
  • Page 57 <Install Path>/vhdl/example/post_sim Create the simprim library. This step is required only once, the first time you perform a simulation: vlib simprim vcom -93 -work simprim <Xilinx Install Path>/vhdl/src/simprims/simprim_Vpackage_mti.vhd vcom -93 -work simprim <Xilinx Install Path>/vhdl/src/simprims/simprim_Vcomponents_mti.vhd vcom -93 -work simprim <Xilinx Install Path>/vhdl/src/simprims/simprim_VITAL_mti.vhd...
  • Page 58 Chapter 7: Timing Simulation www.xilinx.com PCI v3.0.151 Getting Started Guide UG157 August 31, 2005...

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