R
VHDL
1.
2.
3.
4.
48
Start Synplify and choose File > New, or use the new file icon on the toolbar. The New
dialog box appears.
Figure 5-12: Create a New Project
Under File Type, select Project File and enter the project name (flowtest in this example)
and synthesis directory:
<Install Path>/vhdl/example/synthesis
Click OK to exit the dialog box and return to the project window.
Figure 5-13: Main Project Window
To add source files to the new project, click Add.
The first file (used by any design that instantiates Xilinx primitives) is located in:
<Synplicity Install Path>/lib/xilinx
www.xilinx.com
Chapter 5: Synthesizing a Design
PCI v3.0.151 Getting Started Guide
UG157 August 31, 2005
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