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μ
PD720210
2. Pin Function
This section describes each pin function.
Strapping information in the tables shows how the pin can be used to configure the functional settings of this
controller when the pin is pulled up/down, as detected at the end of chip reset. Refer to Chapter 5 for a
complete description of all available pin strap settings. Also refer to Section 3.4 for a list of chip configuration
settings available via external SPI ROM (optional).
2.1
Power Supply
Pin Name
5, 11, 14,
22, 28, 31,
VDD10
47, 64, 67,
70
8, 17, 25,
VDD33
34, 42, 61,
76
AVDD33
71
V50IN
49
V33OUT
48
AVDD33R
50
NGDRV
52
PGDRV
51
ILIM
53
V10FB
54
Note: See section 7.10 for important information about the selection of FET.
R19UH0093EJ0200 Rev.2.00
May 26, 2014
I/O
Pin No.
Type
Power
Power
Power
Power
Power
Power
-
-
-
-
Function
1.05 V power supply for Core Logic
3.3 V power supply for IO buffer
3.3 V power supply for Analog circuit
LDO Regulator 5 V Input
Need to be connected to GND, when integrated LDO is not
used.
LDO 3.3 V Output
μ
15 kΩ and 4.7
F are required between this pin and GND,
when integrated LDO is not used.
SW Regulator 3.3 V Input
SW Regulator Nch FET Control (Note)
SW Regulator Pch FET Control (Note)
SW Regulator Current Sense
SW Regulator Output Monitor
2. Pin Function
Page 6 of 59
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