Clock Settings - Fujitsu 8FX MB2146-510-01-E Setup Manual

3.4.2 BGMA Interface
To start the debug using a BGMA, users shall connect IDC10 socket from the BGMA to CN1 on an
EV-board, and J2 shall be closed to enable reset key S3. Refer to Figure 13.
Debug, normal mode
This setting is effective just when BGMA (MB2146-07-E) is connecting to STK board (MB2146-
510-E). The other BGMA circuit is different from MB2146-07-E. When STK board connects to oth-
er BGMA that may broke the MCU of STK board, so please use the products in this package. For
the package information please refer to "1.1 Objective and Deliverable".

3.4.3 Clock Settings

The MB95560H/570H/580H series MCU uses an internal main CR as a clock source by default. Us-
ers can select on-board crystal as a main clock and a sub-clock. Follow the settings below:
Main clock
Sub-clock
3.4.4 Buzzer Module
A buzzer module is provided to demonstrate an 8/16 composite timer output (a continuous mode).
To enable buzzer module, follow the table below:
Buzzer:
BUZ1
12
MCU Mode
Clock
SW3: X1, X0
SW3: X1A, X0A
Modules
SW1: BUZ.
CN1
J2
S3
Figure 13 Debug Interface
Table 2 J2 Setting
Header name
J2
Table 3 SW3 Setting
Header name
Table 4 SW1 Setting
Header name
Settings
J2
Settings
SW3
SW3
Settings
SW1
LED4 BUZ