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No.
Symbol
30
OSCI
31
OSC0
32
VSS
33
NC
34
/NMI(PULL-UP)
35
/RST
36
NC
37
38
/INT0
39
/INT1
40
/CPUIRQ
41
/EJECT
42
/LOAD_SW
43
/MRST
44
/SLEEP
45
WAIT
46
/WAKEUP
47
NC
I
49
50
VDD
51
TEST3
52
TEST2
53
TEST1
54
TEST0
55
FG
56
FEPSENS
57
CPUDTIO
58
SCK
59
(SBD)
60
(SBO)
61
(SBT)
62
UDRX
63
UDTX
64
FEPRES
65
UCRX
66
UCTX
67
NC
68
VDD
69
VSS
70
AVSS
71
Vref-
72
HALFSENS
73
SLEDSENS
74
HITEMP
75
LOTEMP
76
NC
I
78
I/O
I
High-speed OSC input terminal.
O
High-speed OSC output terminal.
-
GND potential supply terminal.
-
No connect terminal.
-
Pull-up connect terminal.
I
HARD RESET input terminal from power supply/HOST.
-
No connect terminal.
I
MN103S26E /INT0 signal terminal.
I
MN103S26E /INT1 signal terminal.
I
MN103S26E /CPUIRQ signal terminal.
I
Eject key terminal. (using interrupt at Stand-by)
OR Signal input terminal of Mechanism SW-1/SW-2.
I
(using interrupt at STAND-BY)
I
NM103S26E N-MRST input terminal.
I
SLEEP Mode signal input terminal from HOST.
I
MN103S26E N-RESET/WAIT signal input terminal.
O
MN103S26E STAND-BY cancellation signal terminal by NTRYCL signal.
-
No connect terminal.
-
Power supply terminal.
O
TEST terminal.
O
FG signal input terminal.
O
AN8709 SENSE signal terminal.
O
AN8709 CPUDTIN signal terminal.
O
AN8709 SCK signal terminal.
I
YDC Flash writer SBD signal terminal.
I
YDC Flash writer SBO signal terminal.
I
YDC Flash writer SBT signal terminal.
I
UART receiving signal terminal. (DEBUG side : not used)
O
UART transmitting signal terminal. (DEBUG side)
O
AN8709 RESETsignal terminal.
I
UART receiving signal terminal. (COMMAND side)
O
UART transmitting signal terminal. (COMMAND side)
-
No connect terminal.
-
Power supply terminal.
-
GND potential supply terminal.
-
ANALOG GND potential supply terminal.
-
ANALOG standard (-) voltage terminal.
I
VHALF power supply terminal.
I
SLED control signal input terminal.
I
High-temperature signal input terminal.
I
Low-temperature signal input terminal.
-
No connect terminal.
- 54 -
INA-N333RS/INA-N333RRS
Terminal Description
TO SCHEMATIC
TO CONTENTS
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