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Texas Instruments TMS320DM642 User Manual

Texas Instruments TMS320DM642 User Manual

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TMS320DM642 EVM OSD FPGA
User's Guide
Literature Number: SPRU295
June 2003

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Summary of Contents for Texas Instruments TMS320DM642

  • Page 1 TMS320DM642 EVM OSD FPGA User’s Guide Literature Number: SPRU295 June 2003...
  • Page 2 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...
  • Page 3 Preface Read This First About This Manual The document gives explains how to use the TMS320DM642 evaluation mod- ule with the on-screen display of the field−programmable gate array. Notational Conventions This document uses the following conventions. Program listings, program examples, and interactive displays are shown in a special typeface similar to a typewriter’s.
  • Page 4 The following books describe the TMS320VC5509 and related support tools. To obtain a copy of any of these TI documents, go to the TI website: www.ti.com. TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor Data Manual (SPRS200) provides timing and electrical specifications for the TMS320DM642.
  • Page 5 DMA (EDMA), expansion bus, clocking and phase-locked loop (PLL), and the power-down modes. Related Documentation From Spectrum Digital DM642 EVM Technical Reference (Spectrum Digital) describes the evalua- tion module for the Texas Instruments TMS320DM642. Trademarks Trademarks are the property of their respective owners.
  • Page 6 Trademarks This page is intentionally left blank.

  • Page 7: Table Of Contents

    ............. . . SPRU295 TMS320DM642 EVM OSD FPGA User’s Guide...
  • Page 8 ......... . . TMS320DM642 EVM OSD FPGA User’s Guide...
  • Page 9 ............SPRU295 TMS320DM642 EVM OSD FPGA User’s Guide...
  • Page 10 Memory Map of OSD FPGA for CE3 Memory Space ......TMS320DM642 EVM OSD FPGA User’s Guide SPRU295...

  • Page 11: Features

    TMS320DM642 OSD FPGA EVM This document describes the operation of the on-screen display (OSD) field programmable gate array (FPGA) used on the TMS320DM642 evaluation module (EVM). The FPGA is a Xilinx XC2S300E−6PQ208C. Features The OSD FPGA has the following features:...

  • Page 12: Osd Fpga System Block Diagram

    FPGA_CCLK DENC_VSYNC VSVGC DENC_FIELD FSVGC FPGA_DONE To LED DENC_BLANK CBOz Composite Out/ TVDETECT HD Out RTS0_A Decoder PIXCLKI (3 RCA Jacks) (SAA7115) PIXCLKI PIXCLKO PIXCLKO RTS0_B DENCDATA[11:0] Decoder S−Video Out PD[11:0] (SAA7115) 94−Pin Mini DIN) TMS320DM642 OSD FPGA EVM SPRU295...

  • Page 13: Osd Fpga Signals

    EXTINT6 to the DSP. Table 1. Signal Definitions Signal Type Description Miscellaneous Signals RESET Asynchronous system reset FLASH_PAGE[2:0] Page bits for flash on EVM LED[7:0] LED outputs which drive LEDs on EVM SPRU295 TMS320DM642 OSD FPGA EVM...
  • Page 14 DM642 EMIF Signals EMIF asynchronous memory write enable/programmable synchronous interface write enable EMIF asynchronous memory output enable/programmable synchronous interface output enable SOE3 EMIF synchronous memory output enable for memory space CE3 EA[22, 7:3] EMIF address bus TMS320DM642 OSD FPGA EVM SPRU295...
  • Page 15 Data for serial control PLL_MC Bit clock for serial control Dual UART Interface UART_INTB, Interrupts from dual UART chip UART_INTA UART_RXRDYB, Receive ready from dual UART chip UART_RXRDYA UART_TXRDYB, Transmit ready from dual UART chip UART_TXRDYA SPRU295 TMS320DM642 OSD FPGA EVM...
  • Page 16 Signal Definitions (Continued) Signal Type Description FPGA Configuration Signals FPGA_INIT Delay configuration, indicate configuration clearing or error FPGA_PROG Asynchronous reset to configuration logic FPGA_DIN Serial configuration data input FPGA_CCLK Configuration clock FPGA_DONE Configuration status and start-up control TMS320DM642 OSD FPGA EVM SPRU295...

  • Page 17: Architecture

    The OSD FPGA interfaces to the DM642 EMIF and video port 2. The FPGA also interfaces to the video encoder, clock PLL, dual UART, GPIOs, and LEDs. The different modules in the OSD FPGA and their functionality are described below. SPRU295 TMS320DM642 OSD FPGA EVM...

  • Page 18: Video Interface (If)

    ECLKOUT2 clock speed of 70 MHz. The synchronous registers include a test register and a clock PLL data register. TMS320DM642 OSD FPGA EVM SPRU295...

  • Page 19: On-Screen Display (Osd) Data First-In, First-Out (Fifo)

    OSD data FIFO, unpacking of OSD data, and multiplexing of video and OSD data. The OSD control logic provides a control signal to control the OSD MUX, un- pack signal to the OSD unpack module, and event enable signal to the DMA event generator. SPRU295 TMS320DM642 OSD FPGA EVM...

  • Page 20: Osd Unpack Module

    The OSD Unpack Module reads data from the OSD Data FIFO and unpacks it into 8-bit data. Whenever the video port bus width is 8 bits wide, the OSD Unpack Module unpacks the data into 8-bit data every other clock cycle. TMS320DM642 OSD FPGA EVM SPRU295...

  • Page 21: Osd Color Look-Up Table(Clut)

    OSD CLUT, the write pointer increments, and points to the next memory location in the OSD CLUT. It is left to the software to ensure that the correct number of writes are performed to the OSD CLUT. SPRU295 TMS320DM642 OSD FPGA EVM...

  • Page 22: On-Screen Display (Osd) Multiplexer (Mux)

    See Figure 7. Figure 7. Video 8-bit, Single-edge Output VP2CLK0 10 clk cycles VP2D(9:2) DENCDATA(7:0) − − − − − − − − − TMS320DM642 OSD FPGA EVM SPRU295...

  • Page 23: Phase-Locked Loop (Pll) Serial Interface (If)

    Read Hold = 3 clock cycles Write Hold = 3 clock cycles Turn around = 3 clock cycles See the TMS320DM642 Video/Imaging Fixed−Point Digital Signal Processor Data Manual (literature number SPRS200) for further information on the EMIF SPRU295 TMS320DM642 OSD FPGA EVM...

  • Page 24: Dsp Asynchronous Write

    DSP Asynchronous Read Setup Strobe Hold ECLKOUT2 DM642_EA DM642_OE DM642_ARE DM642_AWE DM642_ED DSP reads here For CE3 space setting recommendations please see section 3.2. Figure 11 and Figure 12 show the synchronous read and write cycles. TMS320DM642 OSD FPGA EVM SPRU295...

  • Page 25: Dma Transfers

    CE space as 32-bit programmable synchronous memory interface. The DM642 EMIF CE Space Secondary Control Register (CESEC3, DM642 Hex address 0x0180 0054) must have the following values set. See the TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor data SPRU295 TMS320DM642 OSD FPGA EVM...

  • Page 26: Display Event Generation And Processing

    Address Map Table 3 shows the memory map of the OSD FPGA for CE1 memory space. Base address for CE1 memory space is 9000 0000. Addresses specified are in Hex. TMS320DM642 OSD FPGA EVM SPRU295...

  • Page 27: Memory Map Of Osd Fpga For Ce1 Memory Space

    Synchronous Test Register † PLL Data Register † 01C-3C Reserved OSD YSTART Register OSD XSTART Register OSD XSTOP Register OSD YSTOP Register † The synchronous registers can be read reliably at a maximum ECLKOUT2 of 70 MHz. SPRU295 TMS320DM642 OSD FPGA EVM...

  • Page 28: Asynchronous Register Definitions

    Places video clock DLL in reset. The DLL should be reset any time the video clock frequency is changed. CLEAR CLUT Clear Color Look Up Table Does not clear the Color Look Up Table (CLUT). Writing is allowed Clears the CLUT and writing to the CLUT is prohibited TMS320DM642 OSD FPGA EVM SPRU295...

  • Page 29: Dma Threshold Lsb Register

    OSD data. Every time the number of 32-bit words in the OSD Data FIFO drops below DMA threshold and the number of events is less than the events specified in Events-Per-Field register, a DMA event is generated. SPRU295 TMS320DM642 OSD FPGA EVM...

  • Page 30: Dma Threshold Msb Register

    OSD FPGA. It is a read-only register. Figure 16. Interrupt Status Register DLL LOCK UART INTA RTS1B RTS1A PLL TX END UART INTB FIFO URUN R-00 RWC-0 R − Read, RWC − Read and clear on write Note: Name Description Reserved TMS320DM642 OSD FPGA EVM SPRU295...

  • Page 31: Interrupt Enable Register

    Interrupt Enable Register, the DSP is interrupted. This bit is cleared when the OSD data FIFO is no longer empty. Interrupt Enable Register The Interrupt Enable Register controls the interrupts from the OSD FPGA. SPRU295 TMS320DM642 OSD FPGA EVM...

  • Page 32: Gpio Direction Register

    Sets the direction for GPIOn, where n = the GPIO number between 7 and 0 Sets the GPIOn as input Sets the GPIOn as output GPIO Register The GPIO Register either controls or reflects the status of the GPIO signals. TMS320DM642 OSD FPGA EVM SPRU295...

  • Page 33: Led Register

    LED7−0 LED switch. LEDn, where n = number 7−0, turns the LED on or off. Turns the LED on Turns the LED off Flash Page Register The DM642 can write to this register to set the 3 flash page bits. SPRU295 TMS320DM642 OSD FPGA EVM...

  • Page 34: Fpga Version

    FPGA Version These bits define the FPGA version number. Synchronous Register Definitions Test Register The DM642 can read and write to this register to verify proper connections for all the 32 bits of the data bus. TMS320DM642 OSD FPGA EVM SPRU295...

  • Page 35: Pll Data Register

    (PLL1708). The data written in the 16 LSB bits of this register are written to the Clock PLL. The PLL TX END bit is set in the Interrupt Status Register on com- pleting the transmission. SPRU295 TMS320DM642 OSD FPGA EVM...

  • Page 36: Osd Xstart Register

    The OSD XSTART is defined in terms of active pixels. The design maintains an FP_COUNT, which counts active pixels within each line, and an FL_COUNT, which counts active lines within each field. Both the FP_COUNT and FL_COUNT counters start counting from 0. When the FP_CONT = OSD TMS320DM642 OSD FPGA EVM SPRU295...

  • Page 37: Osd Ystart Register

    The OSD XSTOP is defined in terms of active pixels. When the FP_COUNT = OSD XSTOP and FL_COUNT = OSD YSTOP, the OSD multiplexer stops multiplexing OSD data in output video stream. The synchronous registers can be read reliably at a maximum ECLKOUT2 of 70 MHz. Note: SPRU295 TMS320DM642 OSD FPGA EVM...

  • Page 38: Osd Ystop Register

    The synchronous registers can be read reliably at a maximum ECLKOUT2 of 70 MHz. Note: Different Video/OSD Modes of Operation The OSD FPGA acts as a bridge between the Video Port of DM642 and SAA7105 Encoder. The Video Port can be programmed as 8/10/16/20-bit port. TMS320DM642 OSD FPGA EVM SPRU295...
  • Page 39 Step 4: Program the 7-bit CLUT memory by writing to the OSD CLUT ad- dress in the CE3 space. The CLUT is 128 deep. You must be sure that the correct number of writes are made to the OSD CLUT. SPRU295 TMS320DM642 OSD FPGA EVM...
  • Page 40 Step 7: Write to the OSD XSTART, OSD YSTART, OSD XSTOP, and OSD YSTOP registers to set the OSD window size. Step 8: Write to the Events-Per-Field register to set the number of events de- sired per field. TMS320DM642 OSD FPGA EVM SPRU295...
  • Page 41 Output hold time: 3 ns (This output hold time is achieved by phase shifting PIXCLKI from the clock driving the encoder data) FPGA Configuration File Generation Tools Used: Synplify 7.2 for synthesis Xilinx 5.1i for place and route iMPACT from Xilinx for hex file generation SPRU295 TMS320DM642 OSD FPGA EVM...
  • Page 42 Provide a name for the output .hex file and a location. Select “Auto PROM Se- lect”. Give the name of the input .bin file when asked, and select “yes” when asked about generating a PROM file. Then, the iMPACT utility generates a .hex file. TMS320DM642 OSD FPGA EVM SPRU295...
  • Page 43 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments TMDSEVM642 TMDSEVM642-0E...

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