Procedure; E1 (2.048Mb/S) Frequency Accuracy - HP 37718A Installation And Verification Manual

N OT E
Performance Tests
PDH/DSn Internal Transmitter Clock Accuracy & Offset

Procedure

1 Recall the HP37718A/19A DEFAULT SETTINGS as shown on Page 3-
2.
W
2 Connect the 75
Counter. Terminate the Frequency Counter input in 75
connector).
3 Set the
TRANSMIT
shown opposite.
When changing the PDH Rate or Offset value the VCXO takes time to
settle. As a consequence the frequency counter reading will not stabilize
until "VCXO OUTPUT BIT RATE SETTLING" clears from the STATUS
line of the display.

E1 (2.048Mb/s) Frequency Accuracy

4 Adjust the Frequency Counter ATTEN and Trigger Level to obtain a
stable reading and ensure that the frequency counter reading is
between 1023995Hz and 1024005Hz.
5 Select FREQUENCY OFFSET [+50PPM].
6 Adjust the Frequency Counter ATTEN and Trigger Level to obtain a
stable reading and ensure that the frequency counter reading is
between 1024046.5Hz and 1024055.5Hz.
7 Select FREQUENCY OFFSET [-50PPM].
8 Adjust the Frequency Counter ATTEN and Trigger Level to obtain a
stable reading and ensure that the frequency counter reading is
between 1023944Hz and 1023953Hz.
OUT port of the PDH/DSn module to the Frequency
display as
W
(use the T
3-9