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Endace DAG 3.8S User Manual

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DAG 3.8S Card User Guide
EDM01-09

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  • Page 1 DAG 3.8S Card User Guide EDM01-09...
  • Page 2 Endace and any named company, or any sponsorship or endorsement by any named company. Use of the Endace products described in this document is subject to the Endace Terms of Trade and the Endace End User License Agreement (EULA).

  • Page 3: Table Of Contents

    Viewing the DAG card status ..........................29 Interface Status ..............................29 Port Statistics ............................... 30 Status Bits ................................31 ATM Network ..............................31 PoS Network ................................ 31 ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...
  • Page 4 ERF 3. TYPE_ATM ..............................59 ERF 4. TYPE_AAL5..............................60 ERF 10. TYPE_COLOR_HDLC_POS ........................61 Extension Headers (EH) ............................62 Introduction ................................ 62 Troubleshooting Reporting Problems ..............................63 Version History ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 5: Introduction

    Introduction Overview The Endace DAG 3.8S card provides the means to transfer data at the full speed of the network into the memory of the host computer, with zero packet loss, in even worst-case conditions. Further, unlike a Network Interface Card (NIC), Endace products actively manage the movement of network data into memory while only consuming a minimal amount of the host computer's resources.

  • Page 6: Purpose Of This User Guide

    EDM01-09v15 DAG_3.8S_Card_User_Guide Purpose of this User Guide The purpose of this User Guide is to provide you with an understanding of the DAG 3.8S card architecture, functionality and to guide you through the following: Installing the card and associated software and firmware •...

  • Page 7: Card Description

    The DAG 3.8S card is also capable of transmitting packets at 100% line rate on both ports while simultaneously receiving packets at 100% line rate on both ports.

  • Page 8: Battery Removal - Don't Do It

    FIFO before transmission to the host. The diagram below shows the DAG 3.8S card's major components and flow of data: ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 9: Line Types

    EDM01-09v15 DAG_3.8S_Card_User_Guide Line Types It is important that you understand the physical characteristics of the network to which you want to connect. If your configuration settings do not match your network, the DAG 3.8S card will not function as expected. Note: If you are unsure about which of the options listed below to apply to your network, please contact your Network Administrator for further information.

  • Page 10: Extended Functions

    EDM01-09v15 DAG_3.8S_Card_User_Guide Extended Functions Co-Processor The DAG 3.8S card is equipped with a Co-Processor connector which can be used with the optional Endace DAG Co-Processor as a data processing tool. The specifications for the Co-Processor IP filtering/packet classification are: •...

  • Page 11: Installation

    Installation Introduction The DAG 3.8S card can be installed in any free PCIx slot. It operates at 66MHz in PCIx mode but will not operate in 32-bit or 64-bit PCI slots. Although the DAG driver supports up to sixteen DAG cards in one system, the DAG card makes heavy use of PCIx bus data transfer resources.

  • Page 12: Port Connectors

    The upper connector of each pair is used for the transmit signal and the bottom connector of each pair is used for the received signal. The DAG 3.8S also has an 8-pin RJ45 PPS input socket located below the optical port connectors on the card bracket. This is available for connection to an external time synchronization source.

  • Page 13: Fixed Optical Transceivers

    EDM01-09v15 DAG_3.8S_Card_User_Guide Fixed Optical Transceivers Fixed optical transceiver versions (pre Rev G) of the DAG 3.8S are shipped with the 1x9 optics module fitted. If you wish to use a different module you must specify this at the time of ordering.

  • Page 14: Pluggable Optical Transceivers

    EDM01-09v15 DAG_3.8S_Card_User_Guide Pluggable Optical Transceivers Overview Pluggable optical transceiver versions (Rev G onwards) of the DAG 3.8S card support industry standard Small Form-factor Pluggable (SFP) optical transceivers. The transceivers consists of two parts: • Mechanical chassis attached to the circuit board •...

  • Page 15: Power Input

    • low loss output Note: Endace recommends that you do not use a combination of single mode and multi mode fibers and optics modules on the same link, as the quality of the received signal cannot be guaranteed. If you have no choice but to mix single mode and multi mode you should be aware that a single mode input connected to a multi mode fiber will have some attenuation but may still be acceptable.

  • Page 17: Configuring The Dag Card

    EDM01-09v15 DAG_3.8S_Card_User_Guide Configuring the DAG card Introduction Configuring the DAG 3.8S card ready for capturing data requires the following steps: Setting up the FPGA (page • Preparing the DAG card for use (page • Configuring the DAG Card (page •...

  • Page 18: Setting Up The Fpga

    FPGA each time the DAG card is powered up. The user image can then be programmed into the FPGA either manually or via a script. ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 19: Programming The Fpga

    PP Xilinx not programmed! If a Co-Processor is fitted on this DAG card, refer to EDM02-02 Co-Processor IP Filtering Software Manual for details on how to program the Co-Processor. ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 20: Dagrom

    EDM01-09v15 DAG_3.8S_Card_User_Guide dagrom is a software utility that enables you to configure the FPGA on Endace DAG cards. dagrom The following is a list of options available in dagrom Option Description Use alternate (stable) half. [Default is current half.] Factory / User.

  • Page 21: Dagld

    Before configuring the DAG 3.8S card you must run the following command to set dagconfig the default parameters in the DAG card. This ensures the DAG 3.8S card functions correctly once you begin capturing data. Note: Ensure you run this command each time the FPGA is reprogrammed.

  • Page 22: Configuring The Dag Card

    DAG Software release 3.2 onwards. It has been dagthree replaced with . Both are still valid. Endace recommends that new dagconfig customer use dagconfig ATM output ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 23: Dagconfig Tokens Explained

    For Ethernet only. The DAG 3.8S card operates in either ” mode. “auto_neg” “noauto_neg mode you must connect the DAG 3.8S card directly to a Ethernet switch or card auto_neg with a full-duplex cable, in which case the DAG 3.8S card will perform Ethernet auto- negotiation.
  • Page 24 Sets or unsets equipment loopback. For testing set to mode and normal operation set to mode. noeql Note: mode loops transmit data from the host back to the PCIx bus. Example dagconfig eql dagconfig noeql ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...
  • Page 25 Note: nic/nonic auto_neg/noauto_neg Both options are valid and still can be used. is not supported auto_neg/noauto_neg by some older cards. See auto_neg / noauto_neg. (page ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...
  • Page 26 DAG card. Not configurable. Stream information relates to the setting of (page rxonly Configures the memory hole to only receive. Example dagconfig rxonly ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...
  • Page 27 Alternatively if you want to ensure you capture the whole packet you can set the length to a larger value. Example Setting up a DAG 3.8S card with a snap length of 200 bytes: dagconfig -d0 slen=200 Note: The ERF header is not included in the value.
  • Page 28 Example dagconfig txonly Note: This option is only applicable on firmware images containing TX. varlen/novarlen The DAG 3.8S card is able to capture packets in two ways. They are: Variable length capture ( • varlen Fixed length capture ( ) - (not support on some firmware images) •...
  • Page 29 The MAC address(s) of the DAG card's ports (ethernet cards only). Example Firmware: edag38spci_terf_pci_v2_19 2v1000fg456 2005/10/19 15:04:34 (user) Card Serial: 5214 MAC Address A: 00:00:00:00:00:00 MAC Address B: 00:00:00:00:00:00 MAC Address C: 00:00:00:00:00:00 MAC Address D: 00:00:00:00:00:00 ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 30: Dagconfig Options

    -v,--verbose <level> Display the DAG card version information. -V,--version Note: For cards with more than 2 ports you can select the required port using: - (portnumber) or --(portletter). ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...
  • Page 31 EDM01-09v15 DAG_3.8S_Card_User_Guide For the DAG 3.8S two additional dagconfig sub-options have been added. There are 12 available counters (see list below) however only two can be in use at any one time. These two counters mimic the dagthree options. --counters <c1,c2>...

  • Page 32: Dagthree Options

    Accumulate counter statistics for a number of seconds. -S,--sticky-counters <seconds> Detect card configuration -t,--detect Display SONIC user device ID. -u,--sonicid Increase verbosity. -v,--verbose Display version information. -V,--version ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 33: Viewing The Dag Card Status

    An example of a card locked to a PoS OC3c stream is shown below: bip3 bip2 bip1 label ATM OC12 An example of a card locked to ATM cell stream at OC12c is shown below: bip3 bip2 bip1 label Sync ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 34: Port Statistics

    OC12 PoS An example of a card set to OC12 PoS while the line carries OC3 PoS is shown below: bip3 bip2 bip1 label ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 35: Status Bits

    • Ensure path label is correct as per the payload • Ensure ATM is off and set. sync Ensure PoS scrambling and settings are correct. • ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 36: General Purpose Counters

    ” is the device number of the DAG card) pos_good_frames_A pos_bytes_rcvd_A pos_good_frames_B pos_bytes_rcvd_B 2683706 16777215 2683707 16777215 72675 9674302 72764 9674178 73226 9747316 73226 974322 73225 974250 73225 974240 73225 974630 73225 974640 ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 37: Using Your Dag Card To Capture Data

    By default, runs indefinitely. To stop, use CTRL+C. You can also configure dagsnap dagsnap to run for a fixed time period then exit. ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 38: Dagsnap

    2. The buffer occupancy. Small values indicate no packet loss. 3. The rate at which data is currently being written. Display version information. -V, --version Delay(wait) in seconds before capture and after. -w,--wait SEC ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 39: Capturing Data At High Speed

    EDM01-09v15 DAG_3.8S_Card_User_Guide Capturing data at high speed As the DAG 3.8S card captures packets from the network link, it writes a record for each packet into a large buffer in the host computer’s main memory. To avoid packet loss, the user application reading the record, such as...

  • Page 40: Viewing Captured Data

    (page dagbits Note: decodes and displays ERF header fields and packet contents are displayed dagbits as a Hex dump only. To decode higher level protocols, Endace recommends using a third party application, see Using third party applications (page Examples Test live traffic on dag0, stream 0 for 60 seconds running the lctr, flags and fcs tests:...
  • Page 41 Available tests dagbits include monotonic time-stamp increment and frame checksum (FCS, aka CRC) validation. See the help for further details. dagbits ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 42: Converting Captured Data

    SUNATM DLT, which includes VPI/VCI information. The following example shows how to use to achieve this: dagconvert dagconvert -v -i atm.erf -o atm_filtered.erf -y SUNATM -b "vpi 10 and vci 12" ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 43: Dagconvert

    CHDLC : HDLC PPP_SERIAL : HDLC MTP2 : HDLC ATM_RFC1483 : ATM, AAL5 SUNATM : ATM, AAL5 Note: Not all options are applicable to all DAG cards. ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 44: Using Third Party Applications

    Wireshark can also read ERF formatted data. Note: Transmitting captured data Configuration The DAG 3.8S card is able to transmit as well as receive packets and can capture received traffic while transmitting. This allows you to use capture tools such as dagsnap dagconvert while is sending packets.

  • Page 45: Trace Files

    If you do not have any ERF trace files available, you can use to generate trace files daggen containing simple traffic patterns. This allows the DAG 3.8S card to be used as a test traffic generator. For further information on using...

  • Page 47: Synchronizing Clock Time

    Common synchronization sources include GPS or CDMA (cellular telephone) time receivers. Endace also provides the TDS 2 Time Distribution Server modules and TDS 6 expansion units that enable you to connect multiple DAG cards to a single GPS or CDMA unit.

  • Page 48: Network Time Protocol

    The best synchronization is achieved when the DAG card is synchronized to an external GPS reference clock, and the computer clock is synchronized to a local NTP server. ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 49: Timestamps

    In this way the interpretation of the timestamp does not need to change when higher resolution clock hardware is available. The DAG 3.8S implements the 26 most significant bits which provides a time resolution of 14.9 nanoseconds.

  • Page 50: Dagclock

    The DAG card takes approximately 20 to 30 seconds to re- synchronize. By default, all DAG cards listen for synchronization signals on their RS-422 port, Note: and do not output any signal to that port. ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 51: Dagclock Statistics Reset

    Thu Apr 28 13:32:45 2007 host Thu Apr 28 14:35:35 2007 Thu Apr 28 14:35:35 2007 Note: For a description of the output see Dagclock output explained (page dagclock ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 52: Dagclock Output Explained

    Reset to zero when statistics are reset, see Dagclock Statistics reset. (page Example error Freq -30ppb Phase -60ns Worst Freq 75ppb Worst Phase 104ns ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...
  • Page 53 No active input - free running. Example start Thu Apr 28 13:32:45 2007 host Thu Apr 28 14:35:35 2007 Thu Apr 28 14:35:35 2007 ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 54: Card With Reference

    This is derived directly from an external reference source or distributed through the Endace TDS 2 (Time Distribution Server) module which allows two DAG cards to use a single receiver. It is also possible for more than two DAG cards to use a single receiver by “daisy-chaining”...

  • Page 55: Single Card No Reference

    Total 87039 Bad 0 Singles Missed 0 Longest Sequence Missed 0 start Wed Apr 27 14:27:41 2007 host Thu Apr 28 14:38:20 2007 Thu Apr 28 14:38:20 2007 ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 56: Two Cards No Reference

    Thu Apr 28 14:48:34 2007 No active input - Free running Note: The slave DAG card configuration is not shown as the default configuration will work. ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 57: Synchronizing With Host

    Wed Apr 27 14:27:41 2007 host Thu Apr 28 14:59:14 2007 Thu Apr 28 14:59:14 2007 Note: The slave DAG card configuration is not shown, the default configuration is sufficient. ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 58: Connector Pin-Outs

    TX PPS- TX SERIAL+ RX SERIAL+ TX SERIAL- RX SERIAL- Note: This wiring is the same as an Ethernet crossover cable (Gigabit crossover, All four pairs crossed). ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 59: Data Formats

    ERF records, there is no file header or trailer. This allows for simple concatenation and splitting of files to be performed on ERF record boundaries. For information on other ERF types, please refer to EDM11-01 ERF types. ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 60: Generic Erf Header

    PCIx bus. The loss is recorded between the current record and the previous record captured on the same stream/interface. The color field is explained under the appropriate type details. ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...
  • Page 61 IPV6 Variable Length Record TYPE_RAW_LINK Raw link data, typically SONET or SDH Frame 32-47: Reserved for CoProcess Development Kit (CDK) Users and Internal use TYPE_PAD Pad Record type ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 62: Erf 1. Type_Pos_Hdlc

    Protocol Header. Length may vary depending on protocol, typically 4 bytes. (4 bytes) Payload Payload = rlen - ERF header (16 bytes) - Extension headers (optional) (bytes of record) - Protocol header (4 bytes) ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 63: Erf 3. Type_Atm

    Flags ATM cells should not have the variable length flag set. (1 byte) Payload Payload = 48 bytes of cell + HEC (1 byte) (bytes of cell) ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 64: Erf 4. Type_Aal5

    The rx error flag in the ERF haders is set should the AAL5 crc fail. (1 byte) Payload Payload = rlen - ERF header (16 bytes) - Extension headers (optional) - Protocol header (bytes of (4 bytes) AAL5 frame) ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 65: Erf 10. Type_Color_Hdlc_Pos

    Protocol header. Length may vary depending on protocol. (4 bytes) Payload Payload = rlen - ERF header (16 bytes) - Extension headers (optional) (bytes of record) - Protocol header (4 bytes) ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 66: Extension Headers (Eh)

    The following diagram shows presence of an Extension Header in addition to the ERF record. The following diagram shows presence of two Extension Headers with Bit 7 of the first Extension Header set to '1'. ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

  • Page 67: Troubleshooting

    EDM01-09v15 DAG_3.8S_Card_User_Guide Troubleshooting Reporting Problems If you have problems with a DAG 3.8S card or Endace supplied software which you are unable to resolve, please contact Endace Customer Support at support@endace.com Supplying as much information as possible enables Endace Customer Support to be more effective in their response to you.

  • Page 69: Version History

    The products described in this technical document are in development and have yet to complete final production quality assurance. Released The products described in this technical document have completed development and final production quality assurance. ©2005 - 2008 Endace Technology Ltd. Confidential - Version 14 - June 2008...

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