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Endace DAG 3.7T User Manual

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DAG 3.7T Card User Guide
EDM01-12

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Summary of Contents for Endace DAG 3.7T

  • Page 1 DAG 3.7T Card User Guide EDM01-12...
  • Page 2 Endace and any named company, or any sponsorship or endorsement by any named company. Use of the Endace products described in this document is subject to the Endace Terms of Trade and the Endace End User License Agreement (EULA).

  • Page 3: Table Of Contents

    Connection ID ................................38 HDLC Connections ............................. 38 RAW Connections .............................. 38 Output Record Formats ............................39 Connection Types ..............................39 Hyper-Channel Connection ..........................39 Timeslot Connection ............................39 ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...
  • Page 4 Overview ................................61 IMA Monitor ............................... 61 IMA Transmit..............................62 Using the HDLC Filter ............................63 Using HDLC and IMA Together ..........................63 Synchronizing Clock Time Overview ................................... 65 ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...
  • Page 5 ERF 8. TYPE_MC_RAW_CHANNEL ........................83 ERF 9. TYPE_MC_AAL5 ............................84 ERF 12. TYPE_MC_AAL2 ............................85 Extension Headers (EH) ............................86 Introduction ................................. 86 Troubleshooting Reporting Problems ..............................87 Version History ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 7: Introduction

    The DAG 3.7T is a 16 port, PCI card that allows capture and transmission of data. Supported protocols include raw data (unmapped/unframed), HDLC and ATM over as many as 512 sub-channels, channels and hyper-channels.

  • Page 8: Purpose Of This User Guide

    EDM01-12v18 DAG_3.7T_Card_User_Guide Purpose of this User Guide The purpose of this User Guide is to provide you with an understanding of the DAG 3.7T card architecture, functionality and to guide you through the following: Installing the card and associated software and firmware •...

  • Page 9: Card Description

    EDM01-12v18 DAG_3.7T_Card_User_Guide Card Description The DAG 3.7T cards are PCI bus cards designed for cell and packet capture and generation over IP networks. The key features of the card are: Support for 16 RJ-45 T1/E1 network interfaces in an external pod housing.

  • Page 10: Card Architecture

    The main FPGA can route packets to either the XScale processor before routing onto the host, or directly to the host via the PCI port. The diagram below shows the card’s major components and the flow of data. ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 11: Line Types

    Overview Endace DAG 3.7T card provides the means to transfer data at the full speed of the network into the memory of the host computer, with zero packet loss guaranteed in even worst-case conditions. Further, unlike a Network Interface Card (NIC), Endace products actively manage the movement of network data into memory while only consuming a minimal amount of the host computer's resources.

  • Page 12: Extended Functions

    These functions are described in more detail in Using your DAG card to capture data (page ) later in this User Guide and also in the following documents available from Endace Customer Support at support@endace.com ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 13: Installation

    Installation Introduction A DAG 3.7T card can be installed in any free PCI slot. It is 5V tolerant and operates only in 32-bit 33MHz PCI mode. If you install the card into a slot that is rated for higher speeds it will cause the bus to automatically change to 33MHz.

  • Page 14: Port Connectors

    Pod case - housed in a 5.25 inch drive bay housing. For further details see External Pod (page ). a Pod rackmount chassis - a 1U, 19 in rack housing. For further details see • Chassis (page ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 15: External Pod

    Use a shielded VHDCI ribbon cable rather than the supplied ribbon cable. The Pod and the DAG 3.7T card connect via a VHDCI cable which is supplied with the Pod. The DAG 3.7T card has one VHDCI connector located on the PCI bracket and another on the card itself.

  • Page 16: Pod Rackmount Chassis

    Inspect the contents of the Pod rackmount chassis kit and ensure you have the following items: 1 x Sliding rail kit • 1 x Pod rackmount chassis (PodRMount-37P1 has one Pod or PodRMount-37P2 has • two Pods) ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...
  • Page 17 Press in the release/locking lever on both sides and continue to slide the Pod rackmount chassis into the rack until it will not slide any further. ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...
  • Page 18 If you have an Endace Pod, you are able to use standard E1/T1 cables available from your local electronic stockist. If you do not have an Endace Pod you will need to make the cables up yourself to match the Pod pinouts shown in the following tables.
  • Page 19 You must use a separate tap for each interface. When you have connected the Pod to the DAG 3.7T and the network interfaces to the network, you must configure the card for your specific requirements. This process is...
  • Page 20 Attach the other end of the VHDCI ribbon cable to the VHDCI PCB using the supplied screws. Remove thumb screws and retain. Select which Pod 2 connector location you want to use (front or back). ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...
  • Page 21 Mount the VHDCI PCB in the required location using the existing thumb screws. Mount the Pod PCB in the Pod chassis using four screws (supplied). 10. Replace the top cover (two screws). ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...
  • Page 22 Remove the VHDCI cable connector from the back of the External Pod case (two thumb screws - keep). Remove the front panel (four screws). Remove screws from the sides of the External Pod case (two screws per side) ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...
  • Page 23 EDM01-12v18 DAG_3.7T_Card_User_Guide Separate the two halves of case starting at the front and using moderate force. Remove the Pod PCB from the case (four screws). ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...
  • Page 24 Ensure you use the correct VHDCI connector location, i.e. Pod 1 for the connector • from the Pod 1 PCB, etc. Take care with the VHDCI ribbon cable. • ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 25: Configuring The Dag Card

    EDM01-12v18 DAG_3.7T_Card_User_Guide Configuring the DAG card Introduction Configuring the DAG 3.7T card ready for capturing data requires the following steps: Setting up the FPGA (page • Preparing the DAG card for use (page • Configuring the DAG Card (page •...

  • Page 26: Setting Up The Fpga

    –rvp –d0 –f xilinx/dag37tpci-mixed-erf.bit where "0" is the device number of the DAG card you wish to capture data from Note: The FPGA image does not support transmit. mixed ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 27: Dagrom

    EDM01-12v18 DAG_3.7T_Card_User_Guide dagrom is a software utility that enables you to configure the FPGA on Endace DAG cards. dagrom The following is a list of options available in dagrom Option Description Use alternate (stable) half. [Default is current half.] Factory / User.

  • Page 28: Loading New Firmware Images Onto A Dag Card

    Before configuring the DAG 3.7T card you must run the following command to dagconfig set the default parameters in the DAG card. This ensures the DAG 3.7T card functions correctly once you begin capturing data. Note: Ensure you run this command each time the FPGA is reprogrammed.

  • Page 29: Configuring The Dag Card

    Returning the card to the default configuration means that all the links will have the same settings. You then only need to re-configure those you want to change from the default. ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 30: Configuring The Links

    Configuring the Links Overview Each connected link on the DAG 3.7T Pod must be configured to the requirements of the tapped network. For each link complete the following steps to configure the link. Each link represents a network interface on the 3.7T Pod.
  • Page 31 2. Choose appropriate modes The table below describes the different modes corresponding to line characteristics supported by the DAG 3.7T card. Select the required mode for each link. Note: Ensure that the mode you select matches the physical characteristics of the network to which you want to connect.
  • Page 32 The new settings are applied in the order in which you specify them. e.g. to set the DAG 3.7T card in slot 0, to link 1 to mode = 10, T1 line type, 100Ω twisted pair cable and B8ZS/HDB3 encoding use the following commands:...

  • Page 33: Dagconfig Tokens Explained

    Sets or unsets equipment loopback. For testing set to mode and normal operation set to mode. noeql Note: mode loops transmit data from the host back to the PCI bus. Example dagconfig eql dagconfig noeql ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...
  • Page 34 This enables in-line forwarding without copying the data across the memory holes. Example dagconfig overlap dagconfig nooverlap Note: This option is only applicable on firmware images containing TX. ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...
  • Page 35 This option is only applicable on firmware images containing TX. Short Any packet received shorter than xxx will be flagged as an error. The packet is still received by the host. enabled... noerror Example dagconfig short=xxx ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...
  • Page 36 Alternatively if you want to ensure you capture the whole packet you can set the length to a larger value. Example Setting up a DAG 3.7T card with a snap length of 200 bytes: dagconfig -d0 slen=200 Note: The ERF header is not included in the value.
  • Page 37 EDM01-12v18 DAG_3.7T_Card_User_Guide varlen/novarlen The DAG 3.7T card is able to capture packets in two ways. They are: • Variable length capture ( varlen Fixed length capture ( ) - (not support on some firmware images) • novarlen In variable length (...

  • Page 38: Dagconfig Options

    Sets the verbosity level, from 0 (basic) to 3 (full). -v,--verbose <level> Display the DAG card version information. -V,--version Note: For cards with more than 2 ports you can select the required port using: - (portnumber) or --(portletter). ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 39: Dagthree Options

    DAG Software release 3.2 onwards. It has been dagthree replaced with . Both are still valid. Endace recommends that new customer use dagconfig dagconfig is a software utility used to configure and display statistics.

  • Page 40: Viewing The Dag Card Status

    The output includes a number of status bits as they have occurred since the last read. In our example, the read interval is set to 1 sec via the option. See the Definitions (page ) for a full description of each of the status conditions. ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...
  • Page 41 When using high gain modes ensure the unconnected physical interfaces are not configured to capture HDLC data. If configured, the interfaces will receive noise from the adjacent interfaces, amplify it and generate packets with bit errors. ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 43: Configuring Hdlc Connections

    RAW sub-channel connection, RAW channel connection. Multiple Interfaces If you wish to configure connections on multiple interfaces you need to repeat the configuration procedure for each interface you want to monitor. ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 44: Receive/Transmit

    HDLC packet delimiter (0x7e or 0111 1110). RAW Connections Raw connections are assigned connection ID 0 through to ID 15. On a RAW connection there is no bit unstuffing. ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 45: Output Record Formats

    A timeslot connection is a connection which occupies only one timeslot on one interface at 64 kbps. The line would look like: c chan_format ifc_num ts_num To configure a connection on interface 5, timeslot 16, it the line would look like: ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 46: Sub-Channel Connection

    An 8kbps channel can extends 2 x 8k to 16k, 4 x 8k to 32k, or 7 x 8k to 56k. Note: The DAG 3.7T does not support HDLC transmit on sub-channels. Line Connection A line connection is a connection which occupies all timeslots (i.e. full line rate) on one interface.

  • Page 47: Sub-Channel Raw Connection

    . file. The line would look like: d conn_num To delete connection number 17, the line would look like: d 17 ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 49: Configuring Atm Connections

    Endace software and can be found in the tools sub-directory. To use...

  • Page 50: Receive/Transmit

    (page ) for further information on ERF record formats. Connection Type Output ERF Type Type 7 (-c), (-d), (-h), (-l),(-t), (-f) Type 9 AAL5 Reassembly Type 12 AAL2 Reassembly ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 51: Connection Types

    A line connection is a connection which occupies all timeslots (i.e. full line rate) on one interface. The line would look like: l chan_format ifc_num To configure a line connection on interface 0 it would look like: ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 52: Atm Scrambling On Interface

    In order to configure interface 3 to unscramble ATM cells, the line would look like: HEC Connection on Interface The DAG 3.7T card can correct single bit errors in the HEC field as detailed in the ITU I.432 specification. When an interface is correcting HECs, all connections on the interface will be corrected.

  • Page 53: Configuring Mixed Atm And Hdlc Connections

    All connections will automatically default to receive only. For detailed information on configuring specific HDLC and ATM connections, see Configuring HDLC Connections (page ) and Configuring ATM Connections (page ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 55: Using Your Dag Card To Capture Data

    By default, runs indefinitely. To stop, use CTRL+C. You can also configure dagsnap dagsnap to run for a fixed time period then exit. ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 56: Dagsnap

    2. The buffer occupancy. Small values indicate no packet loss. 3. The rate at which data is currently being written. Display version information. -V, --version Delay(wait) in seconds before capture and after. -w,--wait SEC ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 57: Capturing Data At High Speed

    EDM01-12v18 DAG_3.7T_Card_User_Guide Capturing data at high speed As the DAG 3.7T card captures packets from the network link, it writes a record for each packet into a large buffer in the host computer’s main memory. To avoid packet loss, the user application reading the record, such as...

  • Page 58: Viewing Captured Data

    (page dagbits Note: decodes and displays ERF header fields and packet contents are displayed dagbits as a Hex dump only. To decode higher level protocols, Endace recommends using a third party application, see Using third party applications (page Examples Test live traffic on dag0, stream 0 for 60 seconds running the lctr, flags and fcs tests:...
  • Page 59 Available tests dagbits include monotonic time-stamp increment and frame checksum (FCS, aka CRC) validation. See the help for further details. dagbits ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 60: Converting Captured Data

    SUNATM DLT, which includes VPI/VCI information. The following example shows how to use to achieve this: dagconvert dagconvert -v -i atm.erf -o atm_filtered.erf -y SUNATM -b "vpi 10 and vci 12" ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 61: Dagconvert

    DOCSIS : Ethernet CHDLC : HDLC PPP_SERIAL : HDLC MTP2 : HDLC ATM_RFC1483 : ATM, AAL5 SUNATM : ATM, AAL5 Note: Not all options are applicable to all DAG cards. ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 62: Using Third Party Applications

    Wireshark can also read ERF formatted data. Note: Transmitting captured data Configuration The DAG 3.7T card is able to transmit as well as receive packets and can capture received traffic while transmitting. This allows you to use capture tools such as dagsnap dagconvert while is sending packets.

  • Page 63: Trace Files

    If you do not have any ERF trace files available, you can use to generate trace files daggen containing simple traffic patterns. This allows the DAG 3.7T card to be used as a test traffic generator. For further information on using...

  • Page 65: Configuring Extended Functions

    Note: You can also make a connection to the embedded processor by using the dagema library. For more information on the library please contact Endace Support dagema at support@endace.com. ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 66: Directing Data To The Xscale

    Using the AAL Reassembler The AAL Reassembler allows you to reassemble AAL5 or AAL2 frames on the DAG 3.7T card without involving the host computer in processing. The reassembler receives ATM traffic from the line and then sends it to the host either unchanged, dropped or reassembled into AAL5 or AAL2 frames depending upon the configuration used.

  • Page 67: Using Ima

    For more information on the specific configuration options available for the IMA Monitor, please refer to the EDM04-18 IMA Host API Programming Guide available from Endace Support at support@endace.com IMA Monitor The IMA Monitor is intended for use in wire-tap or monitoring mode.

  • Page 68: Ima Transmit

    You can run to create example dagema_stub groups on two DAG 3.7T cards. Please refer to the EDM04-18 IMA Host API Programming Guide available from Endace Support at support@endace.com for definitions of the API functions.

  • Page 69: Using The Hdlc Filter

    The HDLC filter is designed to allow Layer 2 filtering and filtering on HDLC packets on the DAG 3.7T card without involving the host computer in processing. The filter receives HDLC traffic from the line and then either sends it to the host unchanged or dropped, depending upon the filter configuration used.

  • Page 71: Synchronizing Clock Time

    Common synchronization sources include GPS or CDMA (cellular telephone) time receivers. Endace also provides the TDS 2 Time Distribution Server modules and TDS 6 expansion units that enable you to connect multiple DAG cards to a single GPS or CDMA unit.

  • Page 72: Network Time Protocol

    The best synchronization is achieved when the DAG card is synchronized to an external GPS reference clock, and the computer clock is synchronized to a local NTP server. ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 73: Timestamps

    In this way the interpretation of the timestamp does not need to change when higher resolution clock hardware is available. The DAG 3.7T implements the 27 most significant bits which provides a time resolution of 7.5 nanoseconds.

  • Page 74: Dagclock

    The DAG card takes approximately 20 to 30 seconds to re- synchronize. By default, all DAG cards listen for synchronization signals on their RS-422 port, Note: and do not output any signal to that port. ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 75: Dagclock Statistics Reset

    Thu Apr 28 13:32:45 2007 host Thu Apr 28 14:35:35 2007 Thu Apr 28 14:35:35 2007 Note: For a description of the output see Dagclock output explained (page dagclock ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 76: Dagclock Output Explained

    Highest absolute value of the since statistic collection began. Reset to zero when statistics are reset, see Dagclock Statistics reset. (page Example error Freq -30ppb Phase -60ns Worst Freq 75ppb Worst Phase 104ns ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...
  • Page 77 The DAG card time at the last time pulse. If the DAG card has never been synchronized, the following displays: No active input - free running. Example start Thu Apr 28 13:32:45 2007 host Thu Apr 28 14:35:35 2007 Thu Apr 28 14:35:35 2007 ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 78: Card With Reference

    This is derived directly from an external reference source or distributed through the Endace TDS 2 (Time Distribution Server) module which allows two DAG cards to use a single receiver. It is also possible for more than two DAG cards to use a single receiver by “daisy-chaining”...

  • Page 79: Single Card No Reference

    Total 87039 Bad 0 Singles Missed 0 Longest Sequence Missed 0 start Wed Apr 27 14:27:41 2007 host Thu Apr 28 14:38:20 2007 Thu Apr 28 14:38:20 2007 ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 80: Two Cards No Reference

    Thu Apr 28 14:48:34 2007 host Thu Apr 28 14:48:34 2007 No active input - Free running Note: The slave DAG card configuration is not shown as the default configuration will work. ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 81: Synchronizing With Host

    Wed Apr 27 14:27:41 2007 host Thu Apr 28 14:59:14 2007 Thu Apr 28 14:59:14 2007 Note: The slave DAG card configuration is not shown, the default configuration is sufficient. ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 82: Connector Pin-Outs

    RX PPS- TX PPS- TX SERIAL+ RX SERIAL+ TX SERIAL- RX SERIAL- Note: This wiring is the same as an Ethernet crossover cable (Gigabit crossover, All four pairs crossed). ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 83: Data Formats

    ERF records, there is no file header or trailer. This allows for simple concatenation and splitting of files to be performed on ERF record boundaries. ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 84: Generic Erf Header

    PCI bus. The loss is recorded between the current record and the previous record captured on the same stream/interface. The color field is explained under the appropriate type details. ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...
  • Page 85 TYPE_IPV6 IPV6 Variable Length Record TYPE_RAW_LINK Raw link data, typically SONET or SDH Frame 32-47: Reserved for CoProcess Development Kit (CDK) Users and Internal use TYPE_PAD Pad Record type ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 86: Erf 5. Type_Mc_Hdlc

    (8 bytes) Note: When using this record type with the DAG 3.7T card the Interface number is 0, and the connection number is defined by the programmed context. When using this record type with the DAG 7.1S card the interface number is used for the four ports, and the connection number is the VC identifier, as defined in the EDM01-17 DAG 7.1S Card User Guide.

  • Page 87: Erf 6. Type_Mc_Raw

    31 bytes for time slots 0-31. Slot 16 is signaling information. Framed E1: 30 bytes of data for time slots 1-31, slot 0 used for framing is not captured. Slot 16 is signaling information. ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 88: Erf 7. Type_Mc_Atm

    Protocol header. This field is divided into the following: (4 bytes) Description 0-9: Connection number (0-1023). 512 connections are supported by DAG 3.7T card. For the DAG 7.1S card refer to EDM01-17 DAG 7.1S Card User Guide for details. Refer to the Channelized Configuration > Configuration File.

  • Page 89: Erf 8. Type_Mc_Raw_Channel

    - Protocol header (4 bytes) Note: When using this record type with the DAG 3.7T card the Interface number is 0, and the connection number is defined by the programmed context. When using this record type with the DAG 7.1S card the interface number is used for the four ports, and the connection number is the VC identifier, as defined in the DAG 7.1S Card User Guide.

  • Page 90: Erf 9. Type_Mc_Aal5

    Protocol Header. This field is divided into the following: (4 bytes) Bits Attributes 0-10: Connection number (0-2047). 512 connections are supported by DAG 3.7T card. 11-15: Reserved. 16-19: Physical port (0-15) cell was captured on. Physical ID is interpreted from the firmware perspective.

  • Page 91: Erf 12. Type_Mc_Aal2

    Protocol header. This does not include the 8-bit HEC. (4 bytes) Payload Payload = rlen - ERF header (16 bytes) - Extension headers (optional) (bytes of - Protocol header (8 bytes) AAL5 frame) ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 92: Extension Headers (Eh)

    The following diagram shows presence of an Extension Header in addition to the ERF record. The following diagram shows presence of two Extension Headers with Bit 7 of the first Extension Header set to '1'. ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

  • Page 93: Troubleshooting

    EDM01-12v18 DAG_3.7T_Card_User_Guide Troubleshooting Reporting Problems If you have problems with a DAG 3.7T card or Endace supplied software which you are unable to resolve, please contact Endace Customer Support at support@endace.com Supplying as much information as possible enables Endace Customer Support to be more effective in their response to you.

  • Page 95: Version History

    The products described in this technical document are in development and have yet to complete final production quality assurance. Released The products described in this technical document have completed development and final production quality assurance. ©2005-2008 Endace Technology Ltd. Confidential - Version 18 - November 2008...

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