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Endace DAG 3.7T User Manual

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  • Page 2 EDM01-12: DAG 3.7T Card User Guide Published by: ® Endace Measurement Systems Building 7 17 Lambie Drive PO Box 76802 Manukau City 1702 New Zealand Phone: +64 9 262 7260 Fax: +64 9 262 7261 support@endace.com www.endace.com International Locations New Zealand Americas Europe, Middle East &...
  • Page 3 Disc laimer lst every effort has been made to ensure accuracy, neither Endace Measurement Systems Limited nor any employee of the c ompany, shall be liable on any ground whatsoever to any party in respect of decisions or actions they may make as a resu lt of using this information.

  • Page 5: Table Of Contents

    EDM01-12: DAG 3.7T Card User Guide Table of Contents Chapter 1: Introduction Overview Purpose of this User Guide System Requirements Card Description Card Architecture Extended Functions Chapter 2: Installation Introduction DAG Device Driver Inserting the DAG Card Mounting the Pod...
  • Page 6 EDM01-12: DAG 3.7T Card User Guide Chapter 5: Configuring ATM Connections Overview Configuration File Multiple Interfaces Receive/ Transmit Output Record Formats Connection Types Hyper-Channel Connection [h] Timeslot Connection [c] Line Connection [l] ATM Scrambling on Interface [t] HEC Connection on Interface [f]...

  • Page 7: Chapter 1: Introduction

    EDM01-12: DAG 3.7T Card User Guide Chapter 1: Introduction Endace DAG 3.7T card provides the means to transfer data at the full speed Overview of the network into the memory of the host PC, with zero packet loss guaranteed in even worst-case conditions. Further, unlike a NIC, Endace products actively manage the movement of network data into memory without consuming any of the host PC's resources.
  • Page 8 EDM04-01 Linux FreeBSD Software Installation Guide • EDM 04-02 Windows Software Installation Guide Other Systems For advice on using an operating system that is substantially different from either of those specified above, please contact Endace Customer Support at support@endace.com Version 10: May 2006 ©2005...

  • Page 9: Card Description

    EDM01-12: DAG 3.7T Card User Guide The DAG 3.7T cards are PCI bus cards designed for cell and packet capture Card and generation over IP networks. The key features of the card are: Description • Support for an external pod housing 16 RJ-45 T1/E1 network interfaces, •...

  • Page 10: Card Architecture

    EDM01-12: DAG 3.7T Card User Guide T1 or E1 data is received on up to 16 x RJ-45 interfaces, and passes through Card line interface units. It then feeds immediately into the FPGA for deframing Architecture and demapping into ATM or HDLC frames.

  • Page 11: Extended Functions

    EDM01-12: DAG 3.7T Card User Guide The DAG 3.7T card supports the following extended functions: Extended • Functions AAL2/AAL5 segmentation and reassembly, • Inverse Multiplexing ATM (IMA), • HDLC Filtering. These functions are described in more detail in Chapter 7: Capturing Data later in this User Guide and also in the following documents available from Endace Customer Support at support@endace.com:...
  • Page 12 EDM01-12: DAG 3.7T Card User Guide Version 10: May 2006 ©2005...

  • Page 13: Chapter 2: Installation

    EDM01-12: DAG 3.7T Card User Guide Chapter 2: Installation A DAG 3.7T card can be installed in any free PCI slot. It is 5V tolerant and Introduction operates only in 32-bit 33MHz PCI mode. If you install the card into a slot that is rated for higher speeds it will cause the bus to automatically change to 33MHz.

  • Page 14: Connecting The Pod To The Pc

    Interfaces yourself. If you have an Endace pod you will be able to use standard E1/T1 cables available from your local electronic stockist. If you have another type of pod you will need to make the cables up yourself to match the pod pinouts shown in the following tables.

  • Page 15: Connecting To The Network

    EDM01-12: DAG 3.7T Card User Guide The physical pinouts of the RJ-45 connectors for both the Endace and other Connecting types of pod are shown below: the Interfaces (cont.) Endace Pod Other Pod TX Tip TX Ring TX Ring RX Tip...
  • Page 16 EDM01-12: DAG 3.7T Card User Guide Version 10: May 2006 ©2005...

  • Page 17: Chapter 3: Configuring The Card

    • Configuring the connections, • Capturing data. The DAG 3.7T card uses two integrated Exar Octal T1/E1 Framer Chips which each provide support for up to 8 EI/T1interfaces. The tool dagthree which is supplied with the DAG card allows you to configure the card via the Exar chips for a range of physical line characteristics according to your network requirements.

  • Page 18: Leds And Inputs

    EDM01-12: DAG 3.7T Card User Guide • B8ZS: Bipolar with Eight Zero Substitution (T1 Encoding Line Type: only)/HDB3 Hi-density Bipolar Three zeros(E1 Characteristics only), (cont) • AMI Alternate Mark Inversion. • Externally terminated, Cable Type: • 75Ω unbalanced coaxial cable (E1 only), •...

  • Page 19: Load The Fpga Image

    EDM01-12: DAG 3.7T Card User Guide Note: Before you can configure the card you must first load the card Load the with the appropriate FPGA image for the type of data you want to FPGA Image capture. It is important you understand the protocol used by the network to which you want to connect.

  • Page 20: Mode Options

    EDM01-12: DAG 3.7T Card User Guide The table below describes the different line characteristics associated with Mode Options each of the supported modes. Note: Ensure that the mode you select matches the physical characteristics of the network to which you want to connect.

  • Page 21: Default Configuration

    EDM01-12: DAG 3.7T Card User Guide Before configuring the card for your specific requirements Endace Default recommends that you return the card to the default settings using: Configuration dagthree -d1 default The default output is shown below: links 0-7 noreset E1...

  • Page 22: Interface Statistics

    EDM01-12: DAG 3.7T Card User Guide Using “default” Configuring If you use “ ” any settings you specify earlier in the command line the Links default will be returned to the default factory setting regardless of the setting (cont.) specified. In addition you can not return individual links to the default settings.
  • Page 23 EDM01-12: DAG 3.7T Card User Guide Definitions A definition of each of the status bits is described below: Condition Definition Interface or port number (0-15) LIU Loss of Signal. There is not enough voltage swing on the input line. LIU Alarm Indication Signal.

  • Page 24: Help

    EDM01-12: DAG 3.7T Card User Guide If assistance with configuring the DAG card or any other aspect of Help configuration you can use print a help file by using: dagthree -h Version 10: May 2006 ©2005...

  • Page 25: Chapter 4: Configuring Hdlc Connections

    EDM01-12: DAG 3.7T Card User Guide Chapter 4: Configuring HDLC Connections You can define the HDLC physical channels for the card by using the Overview tool to read a channel configuration file and then create each of the dagchan channels defined in that file.

  • Page 26: Receive/Transmit

    EDM01-12: DAG 3.7T Card User Guide Receive/ By default all new connections will receive. To designate specific Transmit connections to either receive or transmit you must type “ ” on the transmit line of the file immediately before the configuration line for that connection.

  • Page 27: Connection Types

    EDM01-12: DAG 3.7T Card User Guide Connection Hyper-Channel Connection [h] A hyper-channel connection is an HDLC connection which occupies one or Types more timeslots on one interface. This line would look like: h chan_format ifc_num ts_num ts_num ts_num Note: You can use up to 32...

  • Page 28: Timeslot Connection [C]

    One bit equals 8 kbps. For example, one timeslot at 64k consists of 8kbps in a sub-channel. An 8kbps time channel extends 2 x 8k to 16k, 4 x 8k to 32k, or 7 x 8k to 56k. Note: The DAG 3.7T does not support HDLC transmit on sub- channels. Line Connection [l] A line connection is a connection which occupies all timeslots (i.e.

  • Page 29: Line Raw Connection [Lr]

    EDM01-12: DAG 3.7T Card User Guide Connection Line RAW Connection [lr] A line RAW connection with HDLC firmware is a connection which Types ( cont.) occupies all timeslots on one interface. The line would look like: lr chan_format ifc_num To configure a line connection on interface 0 the line would look like:...
  • Page 30 EDM01-12: DAG 3.7T Card User Guide Version 10: May 2006 ©2005...

  • Page 31: Chapter 5: Configuring Atm Connections

    Endace software and can be found in the sub-directory. tools Note: To use to configure ATM channels you must have dagchan either the ATM firmware or the mixed firmware loaded on the card.

  • Page 32: Receive/Transmit

    EDM01-12: DAG 3.7T Card User Guide Receive/ By default all new connections will receive. To designate specific Transmit connections to either receive or transmit you must type “ ” on the transmit line of the file immediately before the configuration line for that connection.

  • Page 33: Timeslot Connection [C]

    EDM01-12: DAG 3.7T Card User Guide All connections below this designator will Interface 0-9. operate in Timeslot Connections Corresponds to RJ-45 receive mode. See note below: connections 0-9 on pod. Channel Type: 0 = default (ATM when the ATM image is...

  • Page 34: Atm Scrambling On Interface [T]

    HEC Connection on Interface [f] The DAG 3.7T card can correct single bit errors in the HEC field as detailed in the ITU I.432 specification. When an interface is correcting HECs, all connections on the interface will be corrected.

  • Page 35: Chapter 6: Configuring Mixed Atm And Hdlc Connections

    EDM01-12: DAG 3.7T Card User Guide Chapter 6: Configuring Mixed ATM and HDLC Connections The mixed firmware image allows you to capture both ATM and HDLC data Using Mixed on the same DAG card. Firmware Note: The mixed firmware does not support transmit. If you wish to transmit data as well as receive you must use either the ATM or the HDLC firmware image.
  • Page 36 EDM01-12: DAG 3.7T Card User Guide Version 10: May 2006 ©2005...

  • Page 37: Chapter 7: Capturing Data

    Overview High Load As the DAG 3.7T card captures packets from the network link, it writes a Performance record for each packet into a large buffer in the host PC’s main memory. Avoiding Packet Loss...
  • Page 38 (lctr of the Extensible Record Format [ERF]. See Chapter 9: Data Formats later in this User Guide for more information on the Endace ERF. Increasing Buffer Size You can increase the size of the host PC buffer to enable it to cope with bursts of high traffic load on the network link.

  • Page 39: Configuring Extended Functions

    EDM01-12: DAG 3.7T Card User Guide Overview Configuring The embedded XScale processor provides the means to perform the following Extended extended functions: Functions • Reassembly of AAL2/AAL5 cells, • Inverse Multiplexing (IMA) monitoring over ATM, • Frame filtering over HDLC.

  • Page 40: Starting The Xscale

    The AAL Reassembler allows you to reassemble AAL5 or AAL2 frames on Using the the DAG 3.7T card without involving the host computer in processing. The reassembler receives ATM traffic from the line and then sends it to the host...

  • Page 41: Using The Ima Monitor

    The HDLC filter is designed to allow Layer 2 filtering and filtering on HDLC Using the packets on the DAG 3.7T card without involving the host computer in HDLC Filter processing. The filter receives HDLC traffic from the line and then either sends it to the host unchanged or dropped, depending upon the filter configuration used.

  • Page 42: Using Hdlc And Ima Together

    EDM01-12: DAG 3.7T Card User Guide You can use the IMA Monitor and the HDLC Filter at the same time by Using HDLC running consecutively. dagimademo daghdlcdemo and IMA Note: Ensure you do not use the “ ” option with the second...

  • Page 43: Chapter 8: Synchronizing Clock Time

    Common synchronisation sources include GPS or CDMA (cellular telephone) time receivers. Endace also provides the TDS 2 Time Distribution Server modules and the TDS 6 units that enable you to connect multiple DAG cards to a single GPS or CDMA unit.

  • Page 44: Timestamps

    EDM01-12: DAG 3.7T Card User Guide ERF files contains a hardware generated timestamp of each packet’s arrival. Timestamps The arrival time can be either the point at which the start of the packet arrives (head) or the point at which the end of the packet arrives (tail).

  • Page 45: Configuration Tools

    EDM01-12: DAG 3.7T Card User Guide The DUCK is very flexible, and can be used with or without an external time Configuration reference. It can accept synchronisation from several input sources, and also Tools be made to drive its synchronisation output from one of several sources.

  • Page 46: Card With Reference

    The DAG 3.7T card also has an LED indicator for synchronisation (PPS) signals. See Chapter 3: Configuring the Card earlier in this User Guide for more information.

  • Page 47: Single Card No Reference

    EDM01-12: DAG 3.7T Card User Guide When a single card is used with no external reference, the card can be Single Card No synchronised to the host PC clock. Most PC clocks are not very accurate by Reference themselves, but the DUCK drifts smoothly at the same rate as the PC clock.
  • Page 48 EDM01-12: DAG 3.7T Card User Guide Synchronising with Each Other Two Cards No Although the master card’s clock will drift against UTC, the cards will still be Reference locked together. This is achieved by connecting the time synchronisation (cont.) connectors of both cards using a standard RJ-45 Ethernet cross-over cable.

  • Page 49: Connector Pin-Outs

    EDM01-12: DAG 3.7T Card User Guide Overview Connector DAG cards have an 8-pin RJ45 connector with two bi-directional RS422 Pin-outs differential circuits, A and B. The PPS signal is carried on circuit A, and the serial packet is connected to the B circuit.
  • Page 50 EDM01-12: DAG 3.7T Card User Guide Version 10: May 2006 ©2005...

  • Page 51: Chapter 9: Data Formats

    DAG Cards produce trace files in their own native format called ERF Overview (Extensible Record Format). The ERF type depends upon the type of connection you are using to capture data. The DAG 3.7T supports the following ERF Types: ERF Type Description TYPE_MC_HDLC:...
  • Page 52 EDM01-12: DAG 3.7T Card User Guide timestamp The time of arrival of the cell, an ERF 64-bit timestamp. See Generic Timestamps in Chapter 8: Synchronising Clock Time earlier in Header (cont.) this User Guide for more information on timestamps. One of the following:...

  • Page 53: Type 5 Record

    EDM01-12: DAG 3.7T Card User Guide The Type 5 M ulti-channel HDLC Frame Record is the same as the normal Type 5 Record ERF Types b ut capture interface is always zero. Note: F ixed length mode is no t supported. RX error is set if any MC header Error bit is set.

  • Page 54: Type 6 Record

    EDM01-12: DAG 3.7T Card User Guide The Type 6 Multi-channel RAW Time Slot Link Data Cell Record is the Type 6 Record same as the normal ERF Types but capture interface is always zero. Note: Fixed length is not supported. RX er ror is set if any MC header error bit is set.

  • Page 55: Type 7 Record

    EDM01-12: DAG 3.7T Card User Guide The Type 7 Multi-channel ATM Cell Record is the same as the norm al ERF Type 7 Record Types but capture interface is always zero. Note: Fixed len gth is not supported. RX error is set if any MC header error bit is set.

  • Page 56: Type 8 Record

    EDM01-12: DAG 3.7T Card User Guide The Type 8 Multi-Channel Raw Link Data Record is the same as the normal Type 8 Record ERF Types but capture interface is always zero. Note: Fixed length is not supported. R X error is set if any MC header error bit is set.

  • Page 57: Type 9 Record

    EDM01-12: DAG 3.7T Card User Guide The Type 9 Multi Channel AAL5 Frame Record is the same as the normal Type 9 Record ERF T ypes but capture interface is always zero. Note: Fixed len gth is not supported. RX error is set if any MC header error bit is set.

  • Page 58: Type 12 Record

    EDM01-12: DAG 3.7T Card User Guide The Type 12 Multi Channel AAL2 Frame Record is the same as the normal Type 12 Record ERF Types but capture interface is always zero. Note: Fixed length is not supported. RX er ror is set if any MC header error bit is set.

  • Page 59: Chapter 10 Troubleshooting

    Reporting you are unable to resolve, please contact Endace Customer Support at Problems support@endace.com Supplying as much information as possible enables Endace Customer Support to be more effective in their respons e to you. T...
  • Page 60 EDM01-12: DAG 3.7T Card User Guide Version 10: May 2006 ©2005...

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