Texas Instruments PanelBus TFP503 Manual
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Texas Instruments PanelBus TFP503 Manual

Texas Instruments PanelBus TFP503 Manual

Hdcp digital receiver
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D
Supports UXGA Resolution (Output Pixel
Rates up to 165 MHz)
D
Digital Visual Interface (DVI) and
High-Bandwidth Digital Content Protection
(HDCP) Specification Compliant
D
True-Color, 24 Bits/Pixel, 48-Bit Dual Pixel
Output Mode, 16.7M Colors at 1 or 2 Pixels
Per Clock
D
Laser-Trimmed (50-Ω) Input Stage for
Optimum Fixed Impedance Matching
D
Skew Tolerant up to One Pixel Clock Cycle
(High Clock and Data Jitter Tolerance)
D
4x Over-Sampling for Reduced Bit-Error
Rates and Better Performance Over Longer
Cables
description
The TFP503 is a Texas Instruments PanelBus flat-panel display product, part of a comprehensive family of
end-to-end DVI 1.0-compliant solutions. Targeted primarily at desktop LCD monitors, DLP and LCD projectors,
and digital TVs, the TFP503 finds applications in any design requiring high-speed digital interface with the
additional benefit of an extremely robust and innovative encryption scheme for digital content protection.
The TFP503 supports display resolutions up to UXGA, including the standard HDTV formats, in 24-bit true color
pixel format. The TFP503 offers design flexibility to drive one or two pixels per clock, supports TFT or DSTN
panels, and provides an option for time-staggered pixel outputs for reduced ground-bounce.
PowerPAD advanced packaging technology results in best-of-class power dissipation, footprint, and ultra-low
ground inductance.
The TFP503 combines PanelBus circuit innovation and unique implementation for HDCP key protection with
TI's advanced 0.18-µm EPIC-5 CMOS process technology to achieve a completely secure, reliable,
low-powered, low-noise, high-speed, digital interface solution.
The TFP503 comes with embedded preprogrammed HDCP keys, thus eliminating the need for an external
storage device to store the HDCP keys or the need for the customer to purchase HDCP keys from the licensing
authority. An encryption scheme ensures that the embedded HDCP keys are encrypted, thus providing highest
level of key security.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Footnotes:
1.
The digital visual interface (DVI) specification is an industry standard developed by the digital display working group (DDWG) for high−speed
digital connection to digital displays. The high−bandwidth digital content protection system (HDCP) is an industry standard for protecting
DVI outputs from being copied. HDCP was developed by Intel Corporation and is licensed by the Digital Content Protection, LLC. The
TFP503 is compliant to the DVI Rev. 1.0 and HDCP Rev. 1.0 specifications.
2.
The TFP503 has an internal voltage regulator that provides the 1.8 V core power supply from the externally supplied 3.3 V supplies.
PanelBus, PowerPAD and EPIC-5 are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
D
Reduced Power Consumption From 1.8-V
Core Operation With 3.3-V I/Os and
Supplies
D
Reduced Ground Bounce Using
1
Time-Staggered Pixel Outputs
D
Lowest Noise and Best Power Dissipation
Using TI 100-Terminal TQFP PowerPAD
Packaging
D
Advanced Technology Using TI's 0.18-µm
EPIC-5 CMOS Process
D
Embedded Preprogrammed
High-Bandwidth Digital Content Protection
(HDCP) Keys
•
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PanelBus HDCP DIGITAL RECEIVER
2
Copyright  2004, Texas Instruments Incorporated
TFP503
SLDS149 − AUGUST 2004
1

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Summary of Contents for Texas Instruments PanelBus TFP503

  • Page 1 Cables description The TFP503 is a Texas Instruments PanelBus flat-panel display product, part of a comprehensive family of end-to-end DVI 1.0-compliant solutions. Targeted primarily at desktop LCD monitors, DLP and LCD projectors, and digital TVs, the TFP503 finds applications in any design requiring high-speed digital interface with the additional benefit of an extremely robust and innovative encryption scheme for digital content protection.
  • Page 2 TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 TQFP PACKAGE (TOP VIEW) OGND QO23 HSYNC AGND VSYNC Rx2+ Rx2− OGND ODCK Rx1+ Rx1− RSVD CTL2 Rx0+ CTL1 Rx0− DGND RxC+ QE23 RxC− QE22 QE21 DDC_SCL QE20 DDC_SDA QE19 DDC_SA QE18 QE17 QE16...

  • Page 3: Functional Block Diagram

    TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 functional block diagram 3.3 V 3.3 V 1.8 V Regulator Internal 50 Ω Termination RED[7:0] RED[7:0] QE[23:0] Channel 2 CH2[9:0] CTL2 CTL2 Rx2+ QO[23:0] Latch Rx2- ODCK GRN[7:0] GRN[7:0] Channel 1 CH1[9:0] Rx1+ HDCP...

  • Page 4: Terminal Functions

    TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 Terminal Functions TERMINAL DESCRIPTION DESCRIPTION NAME AGND Analog ground. Ground reference and current return for analog circuitry. AV DD 82, 85, Analog V DD . Power supply for analog circuitry. Nominally 3.3 V. 88, 91 Bypass capacitor.
  • Page 5 TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 Terminal Functions (Continued) TERMINAL DESCRIPTION DESCRIPTION NAME PGND PLL ground. Ground reference and current return for internal PLL. PIXS Pixel select. Selects between 1- or 2-pixel/clock output mode. During 2-pixel/clock mode, both even pixels, QE[23:0], and odd pixels, QO[23:0], are output in tandem on a given clock cycle.

  • Page 6: Recommended Operating Conditions

    TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 Terminal Functions (Continued) TERMINAL DESCRIPTION DESCRIPTION NAME RxC+ Clock positive receiver input. Positive side of reference clock T.M.D.S. low-voltage signal differential input pair. RxC− Clock negative receiver input. Negative side of reference clock T.M.D.S. low-voltage signal differential input pair.
  • Page 7 TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) dc digital I/O specifications PARAMETER TEST CONDITIONS UNIT High-level digital input voltage (CMOS inputs) V IH 0.7 V DD (see Note 3) Low-level digital input voltage (CMOS inputs) V IL 0.3 V DD...
  • Page 8 TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) ac specifications PARAMETER TEST CONDITIONS UNIT V ID(2) Differential input sensitivity (see Note 8) mVp−p V ID(3) Maximum differential input 1560 mVp−p Analog input intra-pair (+ to −) differential...
  • Page 9 TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 ac specifications (continued) PARAMETER TEST CONDITIONS UNIT 1 pixel/clock ST = Low PIXS = Low C L = 10 pF ST = High OCK_INV = High C L = 10 pF 2 pixel/clock ST = Low PIXS = High...
  • Page 10 TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 timing diagrams t r(2) t f(2) t r(1) t f(1) QE[23:0], QO[23:0], DE, ODCK CTL[2:1], HSYNC, VSYNC Figure 2. Rise and Fall Time of Data and Control Signals Figure 1. Rise and Fall Time of ODCK f (ODCK) ODCK Figure 3.
  • Page 11 TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 timing diagrams (continued) V IH t d(PDLM) t d(PDLA) DFO, ST, PIXS, STAG, Rx[2:0]+, Rx[2:0]−, V IL OCK_INV Figure 10. Minimum Time PD Low Figure 9. Delay From PD Low to High Before Inputs Are Active t sk(CC) Figure 11.
  • Page 12 TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 fundamental operation The TFP503 is a DVI-compliant digital receiver that is used in digital display systems to receive and decode transition-minimized differential-signaling (T.M.D.S.) encoded RGB pixel data streams. High-bandwidth digital content protection (HDCP) receiver functionality provides decryption of the DVI input data streams encrypted at the transmitter, such as TI’s HDCP TFP510 or TFP513 transmitter, to prevent unauthorized viewing or copying of digital content.
  • Page 13 TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 high-bandwidth digital content protection (HDCP) overview (continued) The downstream encryption described in the specification High-bandwidth Digital Content Protection System Specification (Revision 1.0) protects video data passing from the HDCP transmitter to the HDCP receiver via a DVI link.
  • Page 14 TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 TFP503 clocking and data synchronization (continued) The input clock to the TFP503 is conditioned by a PLL (phase-locked-loop) to remove high frequency jitter from the clock. The PLL provides four 10x clock outputs of different phases to locate and sync the T.M.D.S. data streams (4x oversampling).
  • Page 15 TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 TFP503 modes of operation The TFP503 provides system design flexibility and value by providing the system designer with configurable options or modes of operation to support varying system architectures. The following table outlines the various panel modes that can be supported along with appropriate external control pin settings.

  • Page 16: I 2 C Register Map

    TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 TFP503 output driver configurations (continued) Both PDO and PD have internal pullup resistors; so, if left unconnected, they default the TFP503 to normal operating modes. Sync detect. The TFP503 offers an output, SCDT, to indicate link activity. The TFP503 monitors activity on DE to determine if the link is active.
  • Page 17 TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 C register map (continued) Video receiver KSV. This value may be used to determine that the video receiver is HDCP capable. Valid KSVs contain 20 ones and 20 zeros, a characteristic that is verified by video transmitter hardware before encryption is enabled.
  • Page 18 TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 C register map (continued) Subaddress = 1B Read/Write Default = 00 An[31:24] Subaddress = 1C Read/Write Default = 00 An[39:32] Subaddress = 1D Read/Write Default = 00 An[47:40] Subaddress = 1E Read/Write Default = 00 An[55:48]...
  • Page 19 Default = 4C VEN_ID[7:0] Subaddress = C1 Read Only Default = 01 VEN_ID[15:8] This read-only register contains the 16-bit Texas Instruments vendor ID for the TFP503. VEN_ID[15:0] is hardwired to 0x014C. DEV_ID Subaddress = C2 Read Only Default = 01...
  • Page 20 TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 C interface (continued) The start and stop conditions are shown in Figure 16. The high-to-low transition of DDC_SDA while DDC_SCL is high defines the start condition. The low-to-high transition of DDC_SDA while DDC_SCL is high defines the stop condition.
  • Page 21 TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 C interface (continued) Slave Address Sub Address Slave Address Data Data Acknowledge Write From Transmitter Start Condition Read Stop Condition From Receiver Sr Restart Condition Not Acknowledge (SDA High) Figure 19. I C Read Cycle Slave Address Data...
  • Page 22 TFP503 PanelBus HDCP DIGITAL RECEIVER SLDS149 − AUGUST 2004 Thermal Vias 5.8 mm SQ Minimum Figure 21. Recommended Thermal Land Size More information on this package and other requirements for using thermal lands and thermal vias are detailed in the TI application note PowerPAD Thermally Enhanced Package Application Report, TI literature number SLMA002, available via the TI Web pages beginning at URL: http://www.ti.com The following table outlines the thermal properties of the TI 100-terminal TQFP PowerPAD package.

  • Page 23: Packaging Information

    PACKAGE OPTION ADDENDUM www.ti.com 29-Sep-2008 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Type Drawing TFP503PZP ACTIVE HTQFP Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) TFP503PZPG4 ACTIVE HTQFP Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br)

  • Page 27: Important Notice

    IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

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