Marantz AV9000 Service Manual page 26

QK01:CS5394
VCOM MCLKA ADCTL DACTL SCLK
2 7 6 9
1
Serial Output Interface
VREF Voltage Reference
AINL- 5
+
LP Filter +
AINL+ 4
Decimation
-
-
S/H
Comparator
DAC
26
AINR-
+
LP Filter +
27
Decimation
AINR+
-
-
S/H
Comparator
DAC
Calibration
Microcontroller
24 3 25 28 23 22 8
VA AGND AGND AGND VL LGND TSTO1
VOLTAGE REFERENCE VREF 1 28 AGND
COMMON MODE VOLTAGE OUTPUT VCOM 2 27 AINR+
ANALOG GROUND AGND 3 26 AINR-
LEFT CHANNEL ANALOG INPUT+ AINL+ 4 25 AGND
LEFT CHANNEL ANALOG INPUT- AINL- 5 24 VA
ANALOG CONTROL DATA INPUT 6 23
ADCTL VL
ANALOG SECTION CLOCK INPUT MCLKA 7 22 LGND
TEST OUTPUT TSTO1 8 21 TSTO2
CONTROL DATA OUTPUT DACTL 9 20 MCLKD
CALIBRATION CAL 10 19 PDN
DIGITAL SECTION POWER VD 11 18 DFS
DIGITAL GROUND DGND 12 17 S/M
LEFT/RIGHT CLOCK LRCK 13 16 SDATA
SERIAL CLOCK SCLK 14 15 DGND
Power Supply Connections
VA - Analog Power, Pin 24.
Positive analog supply. Nominally +5 volts.
VL - Logic Power, Pin 23.
Positive logic supply for the analog section. Nominally +5 volts.
AGND - Analog Ground, Pins 3, 25, and 28.
Analog ground reference.
LGND - Logic Ground, Pin 22.
Ground reference for the logic portions of the analog section.
VD - Digital Power, Pin 11.
Positive supply for the digital section. Nominally +5 volts.
DGND - Digital Ground, Pins 12 and 15.
Digital ground reference for the digital section.
Analog Inputs
AINR-, AINR+ - Differential Right Channel Analog Inputs, Pins 26 and 27.
Analog input connections for the right channel differential inputs. Nominally 4.0 Vpp
differential for full-scale digital output.
AINL-, AINL+ - Differential Left Channel Analog Inputs, Pins 4 and 5.
Analog input connections for the left channel differential inputs. Nominally 4.0 Vpp
differential for full-scale digital output.
Analog Outputs
VCOM - Common Mode Voltage Output, Pin 2.
Nominally +2.5 volts. Requires a 10 mF electrolytic capacitor in parallel with 0.1 mF
ceramic capacitor for decoupling to AGND. Caution is required if this output be used
to bias the analog input buffer circuits. Refer to the CDB5394 as an example.
VREF - Voltage Reference Output, Pin 1.
Nominally +4 volts. Requires a 100 mF electrolytic capacitor in parallel with 0.1 mF
ceramic capacitor for decoupling to AGND.
All manuals and user guides at all-guides.com
LRCK SDATA MCLKD
Digital Inputs
14 13 16 20 ADCTL - Analog Control Input, Pin 6.
Must be connected to DACTL. This signal enables communication between the analog
PDN
19 and digital circuits.
DFS
DFS - Digital Format Select, Pin 18.
18
The relationship between LRCK, SCLK and SDATA is controlled by the DFS pin.
S/M
17 When high, the serial output data format is I 2 S compatible. The serial data format
CAL is left-justified when low.
10
Digital High CAL - Calibration, Pin 10.
Activates the calibration of the tri-level delta-sigma modulator on the rising edge of
Pass
Filter Filter the CAL input.
MCLKA - Analog Section Input Clock, Pin 7.
This clock is internally divided and controls the delta-sigma modulators. An MCLKA
frequency of 12.288 MHz sets a modulator sampling rate of 3.072 MHz and a output
sample rate of 48 kHz. MCLKA must be connected to MCLKD.
Digital High
MCLKD - Digital Section Input Clock, Pin 20.
Pass
MCLKD clocks the digital filter and must be connected to MCLKA. The required
Filter
Filter
MCLKD frequency is determined by the desired sample rate. A MCLKD of 12.288MHz
corresponds to Fs equal to 48 kHz. MCLKA must be connected to MCLKD.
PDN - Power Down, Pin 19.
When high, the device enters power down. Upon returning low, the device enters
normal operation and issues commands to initialize the voltage reference and
synchronize the analog and digital sections of the device.
21 11 12 15
S/M - Slave or Master Mode, Pin 17.
TSTO2 VD DGND DGND
When high, the device is configured for Slave mode where LRCK and SCLK are
inputs. The device is configured for Master mode where LRCK and SCLK are outputs
when S/M is low.
Digital Outputs
ANALOG GROUND DACTL- Digital to Analog Control Output, Pin 9.
Must be connected to ADCTL. This signal enables communication between the
RIGHT CHANNEL ANALOG INPUT+
digital and analog circuits.
RIGHT CHANNEL ANALOG INPUT-
SDATA - Digital Audio Data Output, Pin 16.
ANALOG GROUND
The 24-bit audio data is presented MSB first, in 2's complement format. This pin has
POSITIVE ANALOG POWER
a internal pull-down resistor and must remain low during the power-up sequence to
ANALOG SECTION LOGIC POWER
avoid accessing a test mode.
ANALOG SECTION LOGIC GROUND
TEST OUTPUT
Digital Inputs or Outputs
DIGITAL SECTION CLOCK INPUT
LRCK - Left/Right Clock, Pin 13.
POWER DOWN LRCK determines which channel, left or right, is to be output on SDATA. The
SERIAL DATA FORMAT SELECT relationship between LRCK, SCLK and SDATA is controlled by the Digital Format
Select (DFS) pin. Although the outputs for each channel are transmitted at different
SLAVE/MASTER MODE
times, Left/Right pairs represent simultaneously sampled analog inputs. In master
SERIAL DATA OUTPUT
mode, LRCK is an output whose frequency is equal to Fs. In Slave Mode, LRCK is
DIGITAL GROUND
an input whose frequency must be equal to Fs.
SCLK - Serial Data Clock, Pin 14.
Clocks the individual bits of the serial data from SDATA. The relationship between
LRCK, SCLK and SDATA is controlled by the Digital Format Select (DFS) pin. In
master mode, SCLK is an output clock at 64•L Fs. In slave mode, SCLK is an input
which requires a continuously supplied clock at any frequency from 48•L to 128•L
Fs (64•L is recommended).
Miscellaneous
TSTO1, TSTO2 - Test Outputs, Pins 8 and 21.
These pins are intended for factory test outputs. They must not be connected to any
external component or any length of circuit trace.
45
Q651:ZR38600
Host
Functional Block Diagram
4
Serial Input Ports
A Serial Serial
E Audio Host
Inputs Interface
F
S/PDIF
S/PDIF Input
Receiver
Parallel Port
4
Control
Parallel
Host
Interface
Input
16
Data
FIFO
8 x 9
System
Memory ICE
Oscillator
Interface Interface
& DSP PLL
20
Address
4
Test
Pin 1 index mark,
notched corner, or both 100 81
1 80
A0
GND
SS
TMS
INT
VDD
D14/RDY
GND
A1
A2
A3
VDD
D13/ C/D
MUTE/GPIO5
D12/ERR
A4
VDD
GPIO4 ZR38600
GND
(TOP VIEW)
A5
A6
D11/PP7
GPIO3
A7
A8
D10/PP6
A9
A10
GND
VDD
30 51
31 50
Instruction Unit Program Sequence Unit Address Generation Unit
20 Program Address Bus
20 Data Address Bus
Repeat
Loop Count
Count Stack
A
A0-7, I0-7,
M0-7, SP
I
Address
Compare
Register
M
File
Instruction
Register
Program Counter
Loop End 3 x 8 x 20
Stack
1 x 20
Mux Increment
32 20
20 Loop Start
Stack 20
1 1 20
Status MS Data Shifter DS
Mode Register
48
Z Register 48
20
Multiplier
42
20
20 x 20
Host Serial Host I/F 48
4 48
ALU
Test ICE I/F
48
4
48 Barrel 48
Interrupt Mask
Shifter
INT External Interrupt
2 x 48
RESET Reset
SD
2 Clock PLLs &
Xtal
Oscillators
3
Clocks &
Control
System Interfaces Arithmetic Unit
Detailed Block Diagram
46
Internal Data Internal Internal
RAM Program RAM Program/ Data
ROM
9k x 20 1k x 32
16k x 32
Serial Output Ports
S/PDIF
Transmitter
ZR38001 Left/Right
G
(S/PDIF)
DSP Core
B
Left/Right
Serial
Left Surround/
C
Audio
Right Surround
Outputs
Center/
Audio
D
Subwoofer
PLL
GPIO
6
General Purpose I/O Ports
Xtal
SDB
SDC
GND
A19
A18
A17
D18
D19
CLKOUT
GND
VDDA
FLTCAP
GNDA
VDD
SCKIN
GND
XTI
XTO
P/M
SPFRX
BYPASS
VDD
DREQ/GPIO0
ERROR/GPIO1
GPIO2
VDD
SDD
GND
CS
WR
Memory
20
Addr
Mux
20 Memory 4
14 Interface
Control
AALU Control
20
10 14
20
Program/Data
Program/Data
Data RAM
RAM
ROM
20
9k x 20 9
1k x 32
16k x 32 Data FIFO
Parallel
8 x 9
Port
Parallel
2
Demux Port
Control
32 32
32 Program Data Bus
12
16
18
DBX
Data
20 12
20 Data Bus
2 15
Mux 2
Input Control
3 Control
Output Control
48
20
D0-D1
D2-D7
CRC
Serial
Logic Ports
A Input
Data SRA SDA
Register B Output
SRB SDB
Data
File
SRC SDC C Output
SRD SDD D Output
2 x 48
SRE SDE E Input
6 x 20
F Input
SRF SDF
G Output/
SRG SDG
General
S/PDIF Output
Purpose
GPIO[5:0]
GPIOC[5:0] GPIO[5:0] Ports
S/PDIF
S/PDIF Input
Receiver
S/PDIF
Transmitter
Input/Output Ports