Download  Print this page

Sony CMOS CXP854P60 Specification page 13

8-bit single-chip microcomputer
Hide thumbs

Advertisement

(2) Serial transfer
Item
SCK cycle time
SCK
high and low level widths
SI input set-up time
(referenced to SCK )
SI input hold time
(referenced to SCK )
SCK
SO delay time
Note) For SCK output mode, in addition to output delay time SO capacitance must be 50pF + 1TTL.
Fig. 4. Serial transfer timing
SCK
SI
SO
System
Pin
Input mode
t
SCK
KCY
Output mode
SCK input mode
t
KH
SCK
t
KL
SCK output mode
SCK input mode
t
SI
SIK
SCK output mode
SCK input mode
t
SI
KSI
SCK output mode
SCK input mode
t
SO
KSO
SCK output mode
t
KL
t
SIK
Input data
t
KSO
0.8V
DD
0.2V
DD
(Ta = –10 to +75°C, V
Condition
Min.
1000
8000/fc
4000/fc – 50
t
KCY
t
KH
t
KSI
0.8V
DD
0.2V
DD
Output data
– 13 –
= 4.5 to 5.5V, Vss = 0V)
DD
Max.
400
100
200
200
100
200
100
0.8V
DD
0.2V
DD
CXP854P60
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Advertisement

Table of Contents
loading

  Related Manuals for Sony CMOS CXP854P60