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Sony CMOS CXP854P60 Specification Page 16

8-bit single-chip microcomputer.
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(6) I
2
C bus timing
Item
SCL clock frequency
Bus free time before starting transfer
Hold time for starting transfer
Clock low level width
Clock high level width
Set-up time for repeated transfers
Data hold time
Data set-up time
SDA, SCL rise time
SDA, SCL fall time
Set-up time for transfer completion
Since SCL rise time (max: 300ns) is not considered part of data hold time, allow at least 300ns.
2
Fig. 9. I
C bus transfer data timing
SDA
t
BUF
SCL
t
HD; STA
P
S
2
Fig. 10. I
C device suggested circuit
• A pull-up resistor must be connected to SDA0 (or SDA1), and SCL0 (or SCL1).
• The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300
noise caused by CRT flashover.
Symbol
f
SLC
t
BUF
t
HD; STA
t
LOW
t
HIGH
t
SU; STA
t
HD; DAT
t
SU; DAT
t
R
t
F
t
SU; STO
t
R
t
t
LOW
HD; DAT
2
I
C
device
device
R
R
R
S
S
S
SDA0
(or SDA1)
SCL0
(or SCL1)
(Ta = –10 to +75°C, V
Pin
SCL
SDA, SCL
SDA, SCL
SCL
SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
t
F
t
t
HIGH
SU; DAT
2
I
C
R
R
R
S
P
P
– 16 –
= 4.5 to 5.5V, Vss = 0V)
DD
Condition
Min.
0
4.7
4.0
4.7
4.0
4.7
0
0.25
4.7
t
HD; STA
t
t
SU; STA
SU; STO
St
or less) can be used to reduce spike
CXP854P60
Max.
Unit
100
kHz
µs
µs
µs
µs
µs
µs
µs
1
µs
0.3
µs
µs
P

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